[llvm] [clang] [RISCV] Bump zicfilp to 0.4 (PR #75134)

@@ -736,7 +736,7 @@ R"(All available -march extensions for RISC-V xventanacondops 1.0 Experimental extensions -zicfilp 0.2 This is a long dummy description +zicfilp 0.4 This is a long dummy description topper

[llvm] [clang] [RISCV] Bump zicfilp to 0.4 (PR #75134)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/75134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [libc] [llvm] [libcxx] [clang] [flang] [compiler-rt] [RISCV][MC] Add support for experimental Zimop extension (PR #75182)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/75182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>; def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9), (sequence "X%u", 18, 23))>; +def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> { topperc wrote:

[llvm] [clang] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/74213 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[compiler-rt] [libc] [libcxx] [clang] [llvm] [clang-tools-extra] [flang] [RISCV][MC] Add support for experimental Zimop extension (PR #75182)

topperc wrote: > > > @topperc If I am not mistaken Zicfiss extension uses moprr instructions > > > to get ROP functionality. But Zimop does not limit only the use of > > > Zicfiss extension. They can be redefined and assigned other operations. > > > > > > Right, but won't users be programmin

[clang] 73beefc - [RISCV] Remove 'experimental-' from extension name in diagnostic message.

Author: Craig Topper Date: 2023-12-14T21:54:15-08:00 New Revision: 73beefc5d7608f019e5759c9cfd9105a591df374 URL: https://github.com/llvm/llvm-project/commit/73beefc5d7608f019e5759c9cfd9105a591df374 DIFF: https://github.com/llvm/llvm-project/commit/73beefc5d7608f019e5759c9cfd9105a591df374.diff

[clang] [llvm] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)

topperc wrote: This patch is unfortunately incorrect because Zvfbfmin implies Zfbfmin but the SiFive CPUs that implement Xsfvfwmaccqqq do not implement Zfbfmin. https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@

[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/75760 This is an out of order core with no vector unit. More information: https://www.sifive.com/cores/performance-p450-470 Scheduler model and other tuning will come in separate patches. >From 22fd20164e9d061a451555

[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)

@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning< def warn_target_unrecognized_env : Warning< "mismatch between architecture and environment in target triple '%0'; did you mean '%1'?">, InGroup; +def warn_knl_knm_target_supports_remove : Warning<

[clang] [llvm] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)

topperc wrote: @ebiggers are you table to commit or do you need someone else to do it? I don't recall seeing a commit from you before so I wasn't sure. https://github.com/llvm/llvm-project/pull/74213 ___ cfe-commits mailing list cfe-commits@lists.llvm

[llvm] [clang] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/74213 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Recommit [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (#73765) (PR #75890)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/75890 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)

@@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), [(set GR64:$dst, (load addr:$src))]>; } +def : Pat<(or (and GR64:$dst, -256), topperc wrote: The patterns probably belong in X86InstrCompiler.td whe

[clang] [llvm] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)

@@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 + +define i64 @sub8(i64 noundef %res, ptr %byte) { +; X64-LABEL: sub8: +; X6

[clang] [llvm] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)

@@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 + +define i64 @sub8(i64 noundef %res, ptr %byte) { topperc

[clang-tools-extra] [clang] [llvm] [ISel] Add pattern matching for depositing subreg value (PR #75978)

@@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), [(set GR64:$dst, (load addr:$src))]>; } +def : Pat<(or (and GR64:$dst, -256), topperc wrote: What about GR32? https://github.com/llvm/llvm-project/

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -121,38 +121,36 @@ entry: declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -121,38 +121,36 @@ entry: declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/75760 >From 22fd20164e9d061a451555c5158f0a8ecb73f77e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 17 Dec 2023 18:18:43 -0800 Subject: [PATCH 1/2] [RISCV] Add sifive-p450 CPU. This is an out of order core wit

[clang-tools-extra] [llvm] [clang] [ISel] Add pattern matching for depositing subreg value (PR #75978)

@@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), [(set GR64:$dst, (load addr:$src))]>; } +def : Pat<(or (and GR64:$dst, -256), topperc wrote: I meant GPR32 for the destination type def : Pat<(or (

[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)

@@ -222,6 +222,11 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-pref

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/75760 >From 22fd20164e9d061a451555c5158f0a8ecb73f77e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 17 Dec 2023 18:18:43 -0800 Subject: [PATCH 1/3] [RISCV] Add sifive-p450 CPU. This is an out of order core wit

[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)

@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, [TuneSiFive7, TuneDLenFactor2]>; +def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, +

[clang-tools-extra] [llvm] [RISCV][Zba] Optimize mul with SH*ADD (PR #68144)

@@ -983,6 +983,1299 @@ define i64 @mul81(i64 %a) { ret i64 %c } + +define i64 @mul153(i64 %a) { +; RV64I-LABEL: mul153: topperc wrote: llvm-mca doesn't think this is an improvement for sifive-x280 https://godbolt.org/z/6ahP11xrq https://github.com/llvm/ll

[clang] 1a3b14d - [RISCV] Add C intrinsics for scalar bitmanip and crypto

Author: Craig Topper Date: 2023-11-24T16:17:22-08:00 New Revision: 1a3b14d26152ab7e7352c8e7aa97ec880cdac82d URL: https://github.com/llvm/llvm-project/commit/1a3b14d26152ab7e7352c8e7aa97ec880cdac82d DIFF: https://github.com/llvm/llvm-project/commit/1a3b14d26152ab7e7352c8e7aa97ec880cdac82d.diff

[clang] [llvm] [InstCombine] Set disjoint flag when turning Add into Or. (PR #72702)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/72702 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [InstCombine] Infer disjoint flag on Or instructions. (PR #72912)

topperc wrote: > Also you'll want to do this inside SimplifyDemanded to reuse existing > KnownBits information. Do we do that for other flags already? I based this off Add/Sub. https://github.com/llvm/llvm-project/pull/72912 ___ cfe-commits mailing l

[llvm] [clang] [InstCombine] Infer disjoint flag on Or instructions. (PR #72912)

topperc wrote: Are the KnownBits in SimplifyDemandedBit usable? We have this code ``` if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) || SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.One, LHSKnown, Depth + 1)) {

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, Result.Multilibs = CSKYMultilibs; } +/// Extend the multi-lib re-use selection mechanism for RISC-V. +/// This funciton will try to re-use multi-lib if they are compat

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -0,0 +1,86 @@ +// Test case for scanning input of GCC output as multilib config topperc wrote: Are we using GCC? https://github.com/llvm/llvm-project/pull/73765 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, Result.Multilibs = CSKYMultilibs; } +/// Extend the multi-lib re-use selection mechanism for RISC-V. +/// This funciton will try to re-use multi-lib if they are compat

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, Result.Multilibs = CSKYMultilibs; } +/// Extend the multi-lib re-use selection mechanism for RISC-V. +/// This funciton will try to re-use multi-lib if they are compat

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, Result.Multilibs = CSKYMultilibs; } +/// Extend the multi-lib re-use selection mechanism for RISC-V. +/// This funciton will try to re-use multi-lib if they are compat

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, Result.Multilibs = CSKYMultilibs; } +/// Extend the multi-lib re-use selection mechanism for RISC-V. +/// This funciton will try to re-use multi-lib if they are compat

[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)

@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, Result.Multilibs = CSKYMultilibs; } +/// Extend the multi-lib re-use selection mechanism for RISC-V. +/// This funciton will try to re-use multi-lib if they are compat

[clang] 8f564a1 - [RISCV] Remove reference to non-existant __builtin_riscv_sha512sum0l/__builtin_riscv_sha512sum1l.

Author: Craig Topper Date: 2023-11-29T11:06:49-08:00 New Revision: 8f564a1f30c160635a8225af5d20669ee42b468a URL: https://github.com/llvm/llvm-project/commit/8f564a1f30c160635a8225af5d20669ee42b468a DIFF: https://github.com/llvm/llvm-project/commit/8f564a1f30c160635a8225af5d20669ee42b468a.diff

[clang] [RISCV] Minor improvements/cleanup to target attribute handling. NFC (PR #73851)

@@ -265,11 +264,11 @@ resolveTargetAttrOverride(const std::vector &FeaturesVec, if (I == FeaturesVec.end()) return FeaturesVec; - const std::vector FeaturesNeedOverride(FeaturesVec.begin(), I); + ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I); -

[clang] 3313c25 - [RISCV] Fix a couple copy/paste mistakes in riscv_crypto.h. NFC

Author: Craig Topper Date: 2023-11-29T12:31:46-08:00 New Revision: 3313c256c82e16e6f15a182bbf77ad2d60548a56 URL: https://github.com/llvm/llvm-project/commit/3313c256c82e16e6f15a182bbf77ad2d60548a56 DIFF: https://github.com/llvm/llvm-project/commit/3313c256c82e16e6f15a182bbf77ad2d60548a56.diff

[clang] [RISCV] Minor improvements/cleanup to target attribute handling. NFC (PR #73851)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/73851 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)

@@ -174,15 +174,10 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, bool HasV = llvm::is_contained(Features, "+zve32x"); topperc wrote: Is HasV unused now? https://github.com/llvm/llvm-project/pull/73971

[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/73971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [InstCombine] Infer disjoint flag on Or instructions. (PR #72912)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/72912 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [InstCombine] Infer disjoint flag on Or instructions. (PR #72912)

topperc wrote: > FWIW, Alive2 is complaining about this commit. These patches are not safe > w.r.t. undef. Why not? https://github.com/llvm/llvm-project/pull/72912 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin

[clang] [llvm] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

https://github.com/topperc requested changes to this pull request. https://github.com/llvm/llvm-project/pull/75768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -7,10 +7,10 @@ declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmacc_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { ; C

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -13,7 +13,7 @@ declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1b define @intrinsic_vfwmacc_4x4x4_tu_f32mf2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT:vsetvli zero, a0,

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -349,16 +349,24 @@ multiclass VPseudoSiFiveVMACC; } -multiclass VPseudoSiFiveVQMACC { +multiclass VPseudoSiFiveVQMACCDOD { foreach m = MxListVF8 in let VLMul = m.value in defm NAME : VPseudoSiFiveVMACC; } +multiclass VPseudoSiFiveVQMACCQOQ { + foreach i = [0

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -349,16 +349,24 @@ multiclass VPseudoSiFiveVMACC; } -multiclass VPseudoSiFiveVQMACC { +multiclass VPseudoSiFiveVQMACCDOD { foreach m = MxListVF8 in let VLMul = m.value in defm NAME : VPseudoSiFiveVMACC; } +multiclass VPseudoSiFiveVQMACCQOQ { + foreach i = [0

[clang] [Clang][RISCV] Add missing support for `__builtin_riscv_cpop_32/64` (PR #76256)

topperc wrote: Can we just use __builtin_popcount and __builtin_popcountll directly in the header file? https://github.com/llvm/llvm-project/pull/76256 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/list

[clang] [Clang][RISCV] Add missing support for `__builtin_riscv_cpop_32/64` (PR #76256)

@@ -82,3 +82,29 @@ unsigned int ctz_64(unsigned long a) { return __builtin_riscv_ctz_64(a); } #endif + +// RV32ZBB-LABEL: @cpop_32( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT:[[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]]) +// RV32ZBB-NEXT:ret i32 [[TMP0]] +//

[clang] 31aa7d2 - [RISCV] Use riscv_bitmanip.h in zbb.c. NFC

Author: Craig Topper Date: 2023-12-22T20:10:37-08:00 New Revision: 31aa7d2de018693a6b45c9056a67229c54461b8f URL: https://github.com/llvm/llvm-project/commit/31aa7d2de018693a6b45c9056a67229c54461b8f DIFF: https://github.com/llvm/llvm-project/commit/31aa7d2de018693a6b45c9056a67229c54461b8f.diff

[clang] [Clang][RISCV] Add missing support for `__builtin_riscv_cpop_32/64` (PR #76256)

@@ -82,3 +82,29 @@ unsigned int ctz_64(unsigned long a) { return __builtin_riscv_ctz_64(a); } #endif + +// RV32ZBB-LABEL: @cpop_32( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT:[[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]]) +// RV32ZBB-NEXT:ret i32 [[TMP0]] +//

[clang] [Clang][RISCV] Add missing support for `__riscv_clmulr_32/64` in `riscv_bitmanip.h` (PR #76289)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76289 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Use `__builtin_popcount` in `__riscv_cpop_32/64` (PR #76286)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76286 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

@@ -1722,6 +1722,35 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, isCodeGenOnly = 0, isAsmParserOnly = 1 in def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], "la.tls.gd", "$dst, $src">; +let hasSideEffe

[llvm] [clang-tools-extra] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

@@ -188,3 +188,8 @@ addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction # fence.tso accepts no operands fence.tso rw, rw # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + +.Ltlsdesc_hi0: +jalr x5, 0(a1), %tlsdesc_hi(.Ltlsdesc_hi0)

[clang-tools-extra] [llvm] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

@@ -597,7 +613,10 @@ struct RISCVOperand final : public MCParsedAsmOperand { if (!isImm()) return false; bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); -if (VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO) +if (VK == RI

[clang] Avoid printing overly large integer. (PR #75902)

@@ -17132,6 +17132,10 @@ static bool ConvertAPValueToString(const APValue &V, QualType T, case BuiltinType::WChar_U: { unsigned TyWidth = Context.getIntWidth(T); assert(8 <= TyWidth && TyWidth <= 32 && "Unexpected integer width"); + if (V.g

[clang] Avoid printing overly large integer. (PR #75902)

@@ -17132,6 +17132,10 @@ static bool ConvertAPValueToString(const APValue &V, QualType T, case BuiltinType::WChar_U: { unsigned TyWidth = Context.getIntWidth(T); assert(8 <= TyWidth && TyWidth <= 32 && "Unexpected integer width"); + if (V.g

[clang] [llvm] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -553,29 +560,40 @@ class GetFTypeInfo { } multiclass VPatVMACC info_pairs, ValueType vec_m1> { + list info_pairs, ValueType vec_m1, + bit lmul_follows_vd = 0> { topperc wrote: lmul doesn't follow vd for any of these

[clang] [llvm] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

@@ -349,14 +349,21 @@ multiclass VPseudoSiFiveVMACC; } -multiclass VPseudoSiFiveVQMACC { +multiclass VPseudoSiFiveVQMACCDOD { foreach m = MxListVF8 in let VLMul = m.value in defm NAME : VPseudoSiFiveVMACC; } +multiclass VPseudoSiFiveVQMACCQOQ { + foreach i = [0

[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 diagnostic. (PR #74950)

topperc wrote: Ping https://github.com/llvm/llvm-project/pull/74950 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Refactor checkRVVTypeSupport to use BuiltinVectorTypeInfo. (PR #74949)

topperc wrote: Ping https://github.com/llvm/llvm-project/pull/74949 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)

https://github.com/topperc approved this pull request. Lgtm https://github.com/llvm/llvm-project/pull/75768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Clang] Remove -save-restore from default features. (PR #76390)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)

@@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), "'Zimop' (May-Be-Operations)">; +def FeatureStdExtZcmop : SubtargetFeature<"experi

[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)

@@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), "'Zimop' (May-Be-Operations)">; +def FeatureStdExtZcmop : SubtargetFeature<"experi

[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)

@@ -0,0 +1,30 @@ +//===-- RISCVInstrInfoZcmop.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)

@@ -670,10 +671,18 @@ static llvm::Triple computeTargetTriple(const Driver &D, if (Args.hasArg(options::OPT_march_EQ) || Args.hasArg(options::OPT_mcpu_EQ)) { StringRef ArchName = tools::riscv::getRISCVArch(Args, Target); - if (ArchName.starts_with_insensi

[clang] [RISCV][NFC] Use errorToBool (PR #76429)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76429 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][NFC] Use RISCVISAInfo instead of string comparison (PR #76387)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76387 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Forward --no-relax option to linker for RISC-V (PR #76432)

topperc wrote: Should this also be done in `tools::gnutools::Linker::ConstructJob`? https://github.com/llvm/llvm-project/pull/76432 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Refactor checkRVVTypeSupport to use BuiltinVectorTypeInfo. (PR #74949)

topperc wrote: > Looks good. > > If I understand correctly, you mean that `vbool64_t` should emit diagnosis of > requiring `zve64x` and should not emit error of `zve32x.` Correct. Since vbool64_t requires SEW/LMUL==64 which is only possible with SEW=8 LMUL=1/8, SEW=16 LMUL=1/4 or SEW=32 LMUL=

[clang] [RISCV] Refactor checkRVVTypeSupport to use BuiltinVectorTypeInfo. (PR #74949)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/74949 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 diagnostic. (PR #74950)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/74950 >From 7675400ba14c6b747fd8ed8b821059fbdb54a3ef Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 9 Dec 2023 12:46:48 -0800 Subject: [PATCH 1/2] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 d

[clang] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 diagnostic. (PR #74950)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/74950 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; let Predicates = [HasStdExtZicfiss, IsRV64] in defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">; - -//===--==

[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZhinx[] = {"zhinxmin"}; static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; static const char *ImpliedExtsZicntr[] = {"zicsr"}; +static const char *ImpliedExtsZicfiss[] = {"

[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZhinx[] = {"zhinxmin"}; static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; static const char *ImpliedExtsZicntr[] = {"zicsr"}; +static const char *ImpliedExtsZicfiss[] = {"

[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; let Predicates = [HasStdExtZicfiss, IsRV64] in defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">; - -//===--==

[clang] [riscv] Fix for __riscv_v_fixed_vlen in vector mask types (PR #76510)

topperc wrote: Missing CodeGen tests https://github.com/llvm/llvm-project/pull/76510 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZhinx[] = {"zhinxmin"}; static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; static const char *ImpliedExtsZicntr[] = {"zicsr"}; +static const char *ImpliedExtsZicfiss[] = {"

[clang] 8076ee9 - [RISCV] Use getBuiltinVectorTypeInfo instead of isRVVType.

Author: Craig Topper Date: 2023-12-28T11:15:14-08:00 New Revision: 8076ee9667198c28cfd1ef6dc8f01c3e539549a2 URL: https://github.com/llvm/llvm-project/commit/8076ee9667198c28cfd1ef6dc8f01c3e539549a2 DIFF: https://github.com/llvm/llvm-project/commit/8076ee9667198c28cfd1ef6dc8f01c3e539549a2.diff

[clang] 6cd41dd - [RISCV] Remove isRVVType from Type.h. NFC

Author: Craig Topper Date: 2023-12-28T11:54:50-08:00 New Revision: 6cd41dde88c6b70b1326ac77255f0f0af96c97d8 URL: https://github.com/llvm/llvm-project/commit/6cd41dde88c6b70b1326ac77255f0f0af96c97d8 DIFF: https://github.com/llvm/llvm-project/commit/6cd41dde88c6b70b1326ac77255f0f0af96c97d8.diff

[clang] 6dc5ba4 - [RISCV] Remove XSfcie extension.

Author: Craig Topper Date: 2023-12-28T13:54:15-08:00 New Revision: 6dc5ba4cca72a5c25597722b8a8c7dcff5fb67be URL: https://github.com/llvm/llvm-project/commit/6dc5ba4cca72a5c25597722b8a8c7dcff5fb67be DIFF: https://github.com/llvm/llvm-project/commit/6dc5ba4cca72a5c25597722b8a8c7dcff5fb67be.diff

[clang] [riscv] Fix for __riscv_v_fixed_vlen in vector mask types (PR #76510)

topperc wrote: I also have a patch for this that I started on 6 months ago. Let me dig it up and see how far along it was. I recall there being some tricky issues. https://github.com/llvm/llvm-project/pull/76510 ___ cfe-commits mailing list cfe-commit

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/76548 Instead of only handling vscale x 16 x i1 predicate vectors, handle any scalable i1 vector where the known minimum is divisible by 8. This will be used on RISC-V where we have multiple sizes of predicate types.

[clang] 2dc50d2 - [RISCV] Correct the CHECK prefixes in attr-riscv-rvv-vector-bits-globals.c to use the correct vector size. NFC

Author: Craig Topper Date: 2023-12-28T18:15:12-08:00 New Revision: 2dc50d28414c827b6723ae6b01c20a7fc3f38165 URL: https://github.com/llvm/llvm-project/commit/2dc50d28414c827b6723ae6b01c20a7fc3f38165 DIFF: https://github.com/llvm/llvm-project/commit/2dc50d28414c827b6723ae6b01c20a7fc3f38165.diff

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/76551 This adopts a similar behavior to AArch64 SVE, where bool vectors are represented as a vector of chars with 1/8 the number of elements. This ensures the vector always occupies a power of 2 number of bytes. A co

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