[PATCH] D132342: [X86][AVX512FP16] Relax limitation to AVX512FP16 intrinsics. NFCI

craig.topper added a comment. Should the const change be a separate patch? They feel unrelated. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D132342/new/ https://reviews.llvm.org/D132342 ___ cfe-commits

[PATCH] D134077: [RISCV] Support -mno-implicit-float.

craig.topper created this revision. craig.topper added reviewers: asb, reames, compnerd, rui.zhang. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, kito-cheng, simoncook, arichardson.

[PATCH] D134089: [clang] Mention vector in the description for -mno-implict-float.

craig.topper created this revision. craig.topper added reviewers: efriedma, reames. Herald added a subscriber: StephenFan. Herald added a project: All. craig.topper requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. As far as I understand, thi

[PATCH] D133634: [clang] Allow vector of BitInt

craig.topper added a comment. In D133634#3795044 , @erichkeane wrote: > The CFE Changes look correct, but @eli.friedman/@craig.topper should comment > as to whether this is acceptable. This is acceptable to me. Comment at: clang/lib

[PATCH] D134077: [RISCV] Support -mno-implicit-float.

This revision was automatically updated to reflect the committed changes. Closed by commit rG549231d38e10: [RISCV] Support -mno-implicit-float. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134077/new/ https://reviews.llv

[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:368 +def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, + AssemblerPredicate<(all_of FeatureExtZcb), + "'Zcb' (Shortened format for basic bit

[PATCH] D134177: Add MC support of RISCV Zcd Extension

craig.topper added a comment. Need to add Zcd command lines to compress-rv32d.s Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoC.td:881 let Predicates = [HasStdExtC, HasStdExtD] in { def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm), CompressPa

[PATCH] D134177: Add MC support of RISCV Zcd Extension

craig.topper added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:47 // CHECK-NOT: __riscv_zicbom // CHECK-NOT: __riscv_zicboz Need to update this too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D134176: Add MC support of RISCV Zcf Extension

craig.topper added a comment. Need to add zcf command lines to compress-rv32f.s Comment at: llvm/lib/Target/RISCV/RISCV.td:366 + "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; +def HasStdExtZcf : Predicate<"Subtarget->hasStdExtZcf()">

[PATCH] D134177: Add MC support of RISCV Zcd Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:366 + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; +def HasStdExtZcd : Predicate<"Subtarget->hasStdExtZcf()">, + AssemblerPredica

[PATCH] D134513: [RISCV][Clang] Replace all undef value with poison

craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134513/new/ https://reviews.llvm.org/D134513 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D134513: [RISCV][Clang] Replace all undef value with poison

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134513/new/ https://reviews.llvm.org/D134513 ___

[PATCH] D134177: Add MC support of RISCV Zcd Extension

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. Need to add Zcd command lines to compress-rv32d.s Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134177/new/ https://review

[PATCH] D134176: Add MC support of RISCV Zcf Extension

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. Need to add zcf command lines to compress-rv32f.s Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134176/new/ https://review

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:116 {"zca", RISCVExtensionVersion{0, 70}}, +{"zcb", RISCVExtensionVersion{0, 70}}, +{"zcmp", RISCVExtensionVersion{0, 70}}, Why is `zcb` mixed into this patch? ==

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/test/MC/RISCV/rv32zcmt-Invalid.s:5 +# CHECK-ERROR: error: immediate must be an integer in the range [0, 63] +cm.jt 64 Why no invalid test for cm.jalt? Comment at: llvm/test/MC/RISCV/rv32zcmt-

[PATCH] D134671: [Driver] Prevent Mips specific code from claiming -mabi argument on other targets.

craig.topper created this revision. craig.topper added reviewers: aaron.ballman, erichkeane. Herald added subscribers: StephenFan, atanasyan, arichardson, sdardis. Herald added a project: All. craig.topper requested review of this revision. Herald added a subscriber: MaskRay. Herald added a project

[PATCH] D134671: [Driver] Prevent Mips specific code from claiming -mabi argument on other targets.

craig.topper added inline comments. Comment at: clang/lib/Driver/Driver.cpp:637 // accordingly to provided ABI name. - A = Args.getLastArg(options::OPT_mabi_EQ); + A = Args.getLastArgNoClaim(options::OPT_mabi_EQ); if (A && Target.isMIPS()) { arichardson w

[PATCH] D134671: [Driver] Prevent Mips specific code from claiming -mabi argument on other targets.

craig.topper updated this revision to Diff 463049. craig.topper added a comment. Herald added subscribers: pcwang-thead, s.egerton, simoncook. Address review comments. I didn't test the -march because all of the target I'm familiar with use -march. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D134671: [Driver] Prevent Mips specific code from claiming -mabi argument on other targets.

This revision was automatically updated to reflect the committed changes. Closed by commit rGd1ad006a8f64: [Driver] Prevent Mips specific code from claiming -mabi argument on other… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm

[PATCH] D134176: Add MC support of RISCV Zcf Extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134176/new/ https://reviews.llvm.org/D134176 ___

[PATCH] D134177: Add MC support of RISCV Zcd Extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134177/new/ https://reviews.llvm.org/D134177 ___

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:367 + [FeatureExtZca]>; // TODO: add Zicsr as another dependence +def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt() && !Subtarget->hasStdExtC()">, +

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:367 + [FeatureExtZca]>; // TODO: add Zicsr as another dependence +def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt() && !Subtarget->hasStdExtC()">, +

[PATCH] D134671: [Driver] Prevent Mips specific code from claiming -mabi argument on other targets.

craig.topper added a comment. In D134671#3824644 , @nickdesaulniers wrote: > I don't think it's an issue for us to work around downstream, but this did > regress support for `-mabi=ms` used in UEFI related build scripts. > https://github.com/ClangBuiltL

[PATCH] D135011: Add sin and cos llvm builtins

craig.topper added a comment. Does these support scalable vector types from ARM SVE or RISC-V? I can't remember what the rest of the __builtin_elementwise do. I ask because the backends will probably crash for them. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://rev

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

craig.topper updated this revision to Diff 465152. craig.topper marked 2 inline comments as done. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.o

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

craig.topper updated this revision to Diff 465162. craig.topper added a comment. Use TT.isRISCV64() in AutoUpgrade.cpp Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116735/new/ https://reviews.llvm.org/D116735 Files: clang/lib/Basic/Targets/RISC

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

craig.topper updated this revision to Diff 465165. craig.topper added a comment. Add requested comment to test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116735/new/ https://reviews.llvm.org/D116735 Files: clang/lib/Basic/Targets/RISCV.h l

[PATCH] D135011: Add builtin_elementwise_sin and builtin_elementwise_cos

craig.topper added a comment. In D135011#3835553 , @bob80905 wrote: > - add sve tests to prove compiler doesn't crash Thank you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135011/new/ https://reviews.l

[PATCH] D135011: Add builtin_elementwise_sin and builtin_elementwise_cos

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:607 + T __builtin_elementwise_cos(T x)return the ratio of the adjacent side length over thefloating point types + hypoteneuse sid

[PATCH] D135011: Add builtin_elementwise_sin and builtin_elementwise_cos

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:606 T __builtin_elementwise_ceil(T x) return the smallest integral value greater than or equal to xfloating point types + T __builtin_elementwise_cos(T x)return the rati

[PATCH] D135519: [RISCV] Remove some vsetvli intrinsics under Zve32*.

craig.topper created this revision. craig.topper added reviewers: kito-cheng, eopXD, frasercrmck, rogfer01, reames. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mart

[PATCH] D135519: [RISCV] Remove some vsetvli intrinsics under Zve32*.

This revision was automatically updated to reflect the committed changes. Closed by commit rG6b24bdb4a5ec: [RISCV] Remove some vsetvli intrinsics under Zve32*. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135519/new/ htt

[PATCH] D135011: Add builtin_elementwise_sin and builtin_elementwise_cos

craig.topper added inline comments. Comment at: clang/docs/ReleaseNotes.rst:473 --- +- Add ``__builtin_elementwise_sin`` and ``__builtin_elementwise_cos`` llvm builtins for floating point types only. Drop "llvm" from this sentence.

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116735/new/ https://reviews.llvm.org/D116735 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

craig.topper added a comment. There's also this patch from @frasercrmck https://reviews.llvm.org/D107290 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135894/new/ https://reviews.llvm.org/D135894 ___ cfe

[PATCH] D135930: [X86] Add AVX-NE-CONVERT instructions.

craig.topper added inline comments. Comment at: clang/lib/Headers/immintrin.h:257 +/* FIXME: Change these When _Float16 type is supported */ +#if defined(__AVXNECONVERT__) && defined(__AVX512FP16__) Is this FIXME still relevant? Don't we support _Float16 with S

[PATCH] D135936: [X86] Support -march=raptorlake

craig.topper added inline comments. Comment at: clang/test/CodeGen/target-builtin-noerror.c:129 (void)__builtin_cpu_is("tremont"); + (void)__builtin_cpu_is("raptorlake"); (void)__builtin_cpu_is("westmere"); Was this list once in alphabetical order? =

[PATCH] D135937: [X86] Support -march=meteorlake

craig.topper added inline comments. Comment at: clang/test/CodeGen/target-builtin-noerror.c:129 (void)__builtin_cpu_is("tremont"); + (void)__builtin_cpu_is("meteorlake"); (void)__builtin_cpu_is("westmere"); I think this list was once in alphabetical order

[PATCH] D135936: [X86] Support -march=raptorlake

craig.topper added a comment. Release notes? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135936/new/ https://reviews.llvm.org/D135936 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lis

[PATCH] D135937: [X86] Support -march=meteorlake

craig.topper added a comment. Release notes? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135937/new/ https://reviews.llvm.org/D135937 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lis

[PATCH] D135938: [X86] Add AVX-VNNI-INT8 instructions.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:781 +Builder.defineMacro("__AVXVNNIINT8__"); + Builder.defineMacro("__AVXVNNIINT8_SUPPORTED__"); if (HasAVXVNNI) Why is this define needed? Comment at: clan

[PATCH] D135966: [X86] Use unsigned int for return type of __get_cpuid_max.

craig.topper created this revision. craig.topper added reviewers: RKSimon, pengfei. Herald added a subscriber: StephenFan. Herald added a project: All. craig.topper requested review of this revision. Herald added a project: clang. It looks like gcc's header already uses unsigned int and we should

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

craig.topper added a comment. In D116735#3857705 , @zixuan-wu wrote: > In D116735#3429850 , @craig.topper > wrote: > >> I'm seeing a regression on 401.bzip2 and possibly 471.astar. And I'm not >> seeing large im

[PATCH] D135966: [X86] Use unsigned int for return type of __get_cpuid_max.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG71a9b8833231: [X86] Use unsigned int for return type of __get_cpuid_max. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D135951: [X86] SUPPORT RAO-INT

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:259 + "Support RAO-INT instructions", + [FeatureSSE2]>; def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", -

[PATCH] D135951: [X86] SUPPORT RAO-INT

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:31799 + // We can lower add/sub/or/xor/and into RAO-INT instructions when the result + // is unused. This should probably be in a separate patch. Repository: rG LLVM G

[PATCH] D135951: [X86][1/2] SUPPORT RAO-INT

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:259 + "Support RAO-INT instructions", + [FeatureSSE2]>; def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", -

[PATCH] D136040: [X86] Support PREFETCHI instructions

craig.topper added a comment. There are too many things in this patch. Please up MC layer changes from intrinsic/builtin changes. The RIP optimization probably also be separate. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136040/new/ https://rev

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:256 + if (hasFeature("v")) +// Minium VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64. +return std::pair(2, 1024); Minimum Repository: rG LLVM Github Monor

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D135894/new/ https://reviews.llvm.org/D135894 ___ cfe-commits mailing list c

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

craig.topper added a comment. > In the original review, I'd mentioned that MinVLEN was sometimes zero. That's > still true, but apparently only happens if you specify multiple extensions in > the -target_feature string. So, we can at least test "v" and "zve64x" on > their own before I go figure

[PATCH] D135933: [X86] Add CMPCCXADD instructions.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:781 +Builder.defineMacro("__CMPCCXADD__"); + Builder.defineMacro("__CMPCCXADD_SUPPORTED__"); if (HasAVXVNNI) What is __CMPCCXADD_SUPPORTED__ for? Comment at

[PATCH] D135933: [X86] Add CMPCCXADD instructions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsX86_64.def:138 +TARGET_BUILTIN(__builtin_ia32_cmpccxadd64, "SLLiv*SLLiSLLiIi", "n", "cmpccxadd") #undef BUILTIN #undef TARGET_BUILTIN There was a blank line here. Put it back.

[PATCH] D135933: [X86] Add CMPCCXADD instructions.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8118 +let Predicates = [HasCMPCCXADD, In64BitMode], Constraints = "$dstsrc2 = $dst" in +multiclass CMPCCXADD_BASE Opc, string OpcodeStr> { craig.topper wrote: > This feels like

[PATCH] D135938: [X86] Add AVX-VNNI-INT8 instructions.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8141 + i128mem, X86vpdpbssd, SchedWriteVecIMul.XMM, + 1>, T8XD; + defm VPDPBSSDY : avx_dotprod_rm<0x50,"vpdpbssd", v8i32, VR2

[PATCH] D139701: [Clang] Don't emit "min-legal-vector-width"="0" for AMDGPU

craig.topper added a comment. Please update the title Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139701/new/ https://reviews.llvm.org/D139701 ___ cfe-commits mailing list cfe-commits@lists.llvm.org ht

[PATCH] D139701: [Clang] Emit "min-legal-vector-width" attribute for X86 only

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139701/new/ https://reviews.llvm.org/D139701 ___

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) Why do we need to touch CMake file that aren't RISC-V? ===

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) fpetrogalli wrote: > lenary wrote: > > craig.topper wrote: > > > Why

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:629 { -if (DefaultPolicy == TAIL_AGNOSTIC) - Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType)); -IntrinsicTypes = {ResultType, Ops[3]->getType()}; -

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added a comment. In D137517#4012298 , @pcwang-thead wrote: > In D137517#4009175 , @fpetrogalli > wrote: > >> @pcwang-thead, I addressed some of your comments. >> >> The value of `EnumFeatures` is no

[PATCH] D140661: [NFC][Clang] Reduce for-loop with SmallVector utility

craig.topper added a comment. Please add [RISCV] to title Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140661/new/ https://reviews.llvm.org/D140661 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[PATCH] D140661: [NFC][Clang][RISCV] Reduce for-loop with SmallVector utility

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140661/new/ https://reviews.llvm.org/D140661 ___

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:862 + Value *VLOperand = Ops[PtrOperandIdx + 1]; + Operands.append(NF, PassThruOperand); + Operands.push_back(PtrOperand); This doesn't look right to me. This

[PATCH] D140678: [RISCV][WIP] Use SmallVector::append to replace some for loops in intrinsic creation. NFC

craig.topper created this revision. craig.topper added a reviewer: eopXD. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-j

[PATCH] D140678: [RISCV][WIP] Use SmallVector::append to replace some for loops in intrinsic creation. NFC

This revision was automatically updated to reflect the committed changes. Closed by commit rG6d323e7e51c6: [RISCV] Use SmallVector::append to replace some for loops in intrinsic creation. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

craig.topper added a comment. So if I read this correctly, the effect of this is that we never pass `-target-cpu` to the backend after this patch and will only pass `-target-feature` and `-tune-cpu`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

craig.topper added a comment. This doesn't seem correct What's the priority among those options for now(w/o this patch)? Pipeline model: Take from -mtune if present. Take from -mcpu if present Use the default pipeline model: generic-rv32 or generic-rv64 Architecture extension:

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:97 bool HasRV32 = false; + bool HasStdExtZvkb = false; + bool HasStdExtZvkg = false; This needs to be rebased, it's all autogenerated by tablegen now. Repository: rG L

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/test/MC/RISCV/rvv/rv64zvkns.s:59 + +vaeskf1.vi v10, v9, 1 +# CHECK-INST: vaeskf1.vi v10, v9, 1 ego wrote: > If I replaces "v10" with "v0", the test fails with an assertion failure. My > own patch uses a slight

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu kito-cheng wrote: > craig.topper wrote: > > I won

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:572 + string default_march = "", + list tunef = []> : ProcessorModel { + string DefaultMarch = default_march; 80 columns

[PATCH] D140950: [X86] Support -march=emeraldrapids

craig.topper added inline comments. Comment at: clang/docs/ReleaseNotes.rst:810 - Support intrinsics of ``_mm(256)_reduce_(max|min)_ep[i|u]8/16``. +- ``-march=emeraldrapids`` is now supported. Can this be on the same link as the other CPUs above? ===

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c:3 // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1579 + llvm::Function *F = +CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty}); + return Builder.CreateCall(F, Metadata); pcwang-thead wrote: > Th

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

craig.topper added a comment. Please split vmulh* from vmul.c. Remove the vmul tests from the handcrafted vmul.c and vmul-eew64.c. Rename those to vmulh.c and vmulh-eew64.c Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141198/new/ https://reviews.

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 ___

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM as far as I'm able to review in phabricator Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141198/new/ https://reviews.llvm.org/

[PATCH] D141459: [RISCV] Use Zvl*b as a lower bound for VScaleRange.

craig.topper created this revision. craig.topper added reviewers: reames, frasercrmck, rogfer01, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, ctetreau, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

craig.topper added inline comments. Comment at: clang/docs/ReleaseNotes.rst:792 - Native detections via ``-mcpu=native`` and ``-mtune=native`` are supported. +- Fix interaction of ``-mcpu`` and ``-march``, RISC-V back-end will take the + architecture extension union of ``-mcpu`

[PATCH] D137266: [RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC

craig.topper created this revision. craig.topper added reviewers: reames, frasercrmck, rogfer01, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbe

[PATCH] D137280: [RISCV] Prevent autovectorization using vscale with Zvl32b.

craig.topper created this revision. craig.topper added reviewers: reames, frasercrmck, rogfer01, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbe

[PATCH] D137280: [RISCV] Prevent autovectorization using vscale with Zvl32b.

craig.topper added a comment. In D137280#3903292 , @reames wrote: > LGTM > > I'm fine with this, but I thought we didn't support zve32f during compilation > at all right now? Is this the only issue which needs fixed. I think zve32f works fine with Zvl6

[PATCH] D137266: [RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC

This revision was automatically updated to reflect the committed changes. Closed by commit rG6254495c6b4f: [RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.l

[PATCH] D137280: [RISCV] Prevent autovectorization using vscale with Zvl32b.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb6ad7ab89ef5: [RISCV] Prevent autovectorization using vscale with Zvl32b. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D137317: [X86][CET] Add Diags for targets pre to i686

craig.topper added a comment. In D137317#3905643 , @nickdesaulniers wrote: > Seems fine, though looking at `llvm::X86::CPUKind`, why do you choose > `llvm::X86::CK_PentiumPro` as the lower bounds? Surely > `llvm::X86::CK_Pentium2` doesn't support CET?

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:437 + +// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s reames wrote:

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added a comment. Do these need their own DecoderNameSpace? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added a comment. In D137350#3906234 , @reames wrote: > In D137350#3906126 , @craig.topper > wrote: > >> Do these need their own DecoderNameSpace? > > What is a decoder namespace? Some quick grepping

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/CMakeLists.txt:18 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget) +tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def) Should not this only be in the CMakeLists for the Tar

[PATCH] D134089: [clang] Mention vector in the description for -mno-implict-float.

This revision was automatically updated to reflect the committed changes. Closed by commit rG0453857d7402: [clang] Mention vector in the description for -mno-implict-float. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134

[PATCH] D135011: Add builtin_elementwise_sin and builtin_elementwise_cos

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM to me with those formatting fixes. Comment at: clang/test/CodeGen/builtins-elementwise-math.c:337 +void test_builtin_elementwise_cos(float f1, float f2, doub

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:14 +//===--===// +// -XVentanaCondOps +//===--==

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 ___ cfe-commits mailing list c

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

craig.topper updated this revision to Diff 491834. craig.topper added a comment. Address review comment in release notes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142144/new/ https://reviews.llvm.org/D142144 Files: clang/docs/ReleaseNotes.r

[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

craig.topper added a comment. Herald added a subscriber: luke. Please rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131141/new/ https://reviews.llvm.org/D131141 ___ cfe-commits mailing list cfe-co

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

craig.topper updated this revision to Diff 491935. craig.topper added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142144/new/ https://reviews.llvm.org/D142144 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Driver/Op

[PATCH] D142477: [X86] Ensure the _mm_test_all_ones macro does not reuse argument (PR60006)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142477/new/ https://reviews.llvm.org/D142477 ___

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