[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

craig.topper added a comment. In D112102#3074656 , @frasercrmck wrote: > Minor typo in the description: `differnet` > > Does this help with compile times, binary sizes, etc? This reduces the clang binary size by 2.34 megabytes according to my local rel

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

craig.topper updated this revision to Diff 380982. craig.topper added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 Files: clang/include/clang/Basic/riscv_vector.td clang/lib/Sema/

[PATCH] D111692: [RISCV] Remove Zvamo C intrinsics and builtins.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6c6abb1ded8d: [RISCV] Remove Zvamo C intrinsics and builtins. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

This revision was automatically updated to reflect the committed changes. Closed by commit rGe2b7aabb57d5: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll:158 ; CHECK-NEXT:vmv.x.s a0, v8 +; CHECK-NEXT:lui a1, 1048560 +; CHECK-NEXT:or a0, a0, a1 frasercrmck wrote: > What's going on here, do you know? I b

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:141 + // either v or zve* suppaort v instructions + bool hasStdExtV() const { return HasStdExtV || HasStdExtZve32x; } + bool hasStdExtZve32x() const { return HasStdExtZve32x; } -

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:184 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); +Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew)); +Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp)); -

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:182 +def FeatureExtZve32x +: SubtargetFeature<"experimental-zve32x", "HasStdExtZve32x", "true", frasercrmck wrote: > Do we need to define distinct `SubtargetFeature`s for each of

[PATCH] D108422: [NFC][clang] Move remaining part of X86Target.def to llvm/Support/X86TargetParser.def

craig.topper added a comment. I'm not opposed either. Comment at: llvm/include/llvm/Support/X86TargetParser.def:220 + +// FIXME: When commented out features are supported in LLVM, enable them here. +CPU_SPECIFIC("generic", 'A', "") erichkeane wrote: > RKSimon w

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:349 + unsigned VLENMax = 65536; + return std::make_pair(VLENMin / 64, VLENMax / 64); +} Should we move RVVBitsPerBlock to RISCVTargetParser.def? Or some other place that can be s

[PATCH] D108151: [NFC][clang] Use X86 Features declaration from X86TargetParser

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108151/new/ https://reviews.llvm.org/D108151 ___ cfe-commits mailing list cfe-commits

[PATCH] D108661: The maximal representable alignment in LLVM IR is 1GiB, not 512MiB

craig.topper added a comment. Wild speculation. This may be a historical artifact of LoadInst and StoreInst having their getAlignment() function written like this when this limit was created unsigned getAlignment() const { return (1 << (getSubclassDataFromInstruction() >> 1)) >> 1; } B

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:158 + // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly set. + I = Features.find("sse4.2"); Why doesn't this say "not explicitly disabled" like the others above?

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: llvm/lib/Support/X86TargetParser.cpp:531 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; ---

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:160 + // enabled. + I = Features.find("sse4.2"); + if (I != Features.end() && I->getValue() && I guess I don't understand why this is coded differently than mmx, popcnt, and xsave

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrFoldTables.cpp:1852 + { X86::VFCMULCPHZrr, X86::VFCMULCPHZrm, 0 }, + { X86::VFCMULCSHZrr, X86::VFCMULCSHZrm, TB_NO_REVERSE }, { X86::VFMADDPD4Yrr,

[PATCH] D107420: [sema] Disallow __builtin_mul_overflow under special condition.

craig.topper added a comment. In D107420#2969715 , @nickdesaulniers wrote: > In D107420#2929115 , @craig.topper > wrote: > >> In D107420#2929039 , >> @aaron.ballman wro

[PATCH] D108886: Add RISC-V sifive-s51 cpu

craig.topper added a comment. Please upload patches with full context. Using -U99 as documented here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108886/new/ htt

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101 + } else { +RVVBitsMin = RVVVectorBitsMinOpt; +RVVBitsMax = RVVVectorBitsMaxOpt; If clang always emits the attribute, are these options effectively dead for

[PATCH] D105092: [RISCV] Add the tail policy argument to builtins/intrinsics.

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:169 + llvm_anyint_ty, LLVMMatchType<1>], [NoCapture>, IntrReadMem]>, RISCVVIntrinsic; // For unit stride fault-only-first load with mask ---

[PATCH] D105092: [RISCV] Add the tail policy argument to builtins/intrinsics.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2288 + (mask_type V0), + VLOpFrag, (XLenVT GPR:$policy))), + (!cast(inst#"_"#kind#"_"#vlmul.MX#"_MASK") I think t

[PATCH] D109260: [RISCV] Add SiFive core E20

craig.topper added a comment. Are you planning to add more CPUs? I think I'd be willing to accept them all as one patch instead of one small patch for each CPU. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D10

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24 +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) -

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24 +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) -

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: clang/test/Misc/target-invalid-cpu-note.c:195 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76 +// RISCV32: note: va

[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2292 + (op2_type op2_reg_class:$rs2), + (mask_type V0), GPR:$vl, sew, (XLenVT GPR:$policy))>; + Does timm:$policy work down here to

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 ___

[PATCH] D109483: [APInt] Normalize naming on keep constructors / predicate methods.

craig.topper added inline comments. Comment at: llvm/include/llvm/ADT/APInt.h:384 /// value for the APInt's bit width. bool isMaxValue() const { return isAllOnesValue(); } isAllOnes()? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[PATCH] D109483: [APInt] Normalize naming on keep constructors / predicate methods.

craig.topper added a comment. I think I read this patch too closely. I'll leave it up to you how much of this you want to do. Comment at: llvm/include/llvm/IR/Constants.h:206 /// Determine if the value is all ones. bool isMinusOne() const { return Val.isAllOnesValue(); }

[PATCH] D109497: [X86][AVX] Update _mm256_loadu2_m128* intrinsics to use _mm256_set_m128* (PR51796)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109497/new/ https://reviews.llvm.org/D109497 ___

[PATCH] D109483: [APInt] Normalize naming on keep constructors / predicate methods.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109483/new/ https://reviews.llvm.org/D109483 ___

[PATCH] D109658: [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

craig.topper added a comment. Does gcc use the same builtin name? Our general policy is to have the same interface as gcc if we have a builtin. So if gcc has these builtins the should work the same way. For IFMA I think I made them commutable by swapping the operands between the builtin and th

[PATCH] D109658: [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

craig.topper added a comment. In D109658#2996714 , @pengfei wrote: > In D109658#2996412 , @craig.topper > wrote: > >> Does gcc use the same builtin name? Our general policy is to have the same >> interface as gc

[PATCH] D109658: [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

craig.topper added a comment. In D109658#2997395 , @pengfei wrote: > In D109658#2996767 , @craig.topper > wrote: > >> In D109658#2996714 , @pengfei >> wrote: >> >>> In D

[PATCH] D109714: Reduce maximum width of _ExtInt from 2^24-1 to 2^23 to workaround SelectionDAG issue.

craig.topper created this revision. craig.topper added reviewers: aaron.ballman, erichkeane. craig.topper requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. SelectionDAG type legalization requires a power of 2 type with at least as many bits a

[PATCH] D109714: Reduce maximum width of _ExtInt from 2^24-1 to 2^23 to workaround SelectionDAG issue.

craig.topper updated this revision to Diff 372331. craig.topper added a comment. Add comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109714/new/ https://reviews.llvm.org/D109714 Files: clang/docs/ReleaseNotes.rst clang/lib/Sema/SemaType

[PATCH] D109686: Check supported architectures in sseXYZ/avxXYZ headers

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109686/new/ https://reviews.llvm.org/D109686 ___

[PATCH] D109681: [RISCV] add Half-precision test for vle/vse

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109681/new/ https://reviews.llvm.org/D109681 ___

[PATCH] D109721: [IR] Reduce max supported integer from 2^24-1 to 2^23.

craig.topper updated this revision to Diff 372362. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Update clang tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109721/new/ https://reviews.ll

[PATCH] D109714: Reduce maximum width of _ExtInt from 2^24-1 to 2^23 to workaround SelectionDAG issue.

craig.topper abandoned this revision. craig.topper added a comment. Abandoning in favor of D109721 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109714/new/ https://reviews.llvm.org/D109714 __

[PATCH] D109721: [IR] Reduce max supported integer from 2^24-1 to 2^23.

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2fd180bbb9a7: [IR] Reduce max supported integer from 2^24-1 to 2^2

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