@@ -332,43 +332,6 @@ def calculate_arch_features(arch_string):
config.available_features.add("llvm-driver")
-def exclude_unsupported_files_for_aix(dirname):
-for filename in os.listdir(dirname):
-source_path = os.path.join(dirname, filename)
-if os.pat
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/71814
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@@ -332,43 +332,6 @@ def calculate_arch_features(arch_string):
config.available_features.add("llvm-driver")
-def exclude_unsupported_files_for_aix(dirname):
-for filename in os.listdir(dirname):
-source_path = os.path.join(dirname, filename)
-if os.pat
https://github.com/chenzheng1030 approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/71814
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@@ -3412,13 +3416,23 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
@@ -2399,6 +2405,29 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
return AllSpilledToReg;
}
+static void findContinuousLoadStore(ArrayRef CSI,
+Register &MergeFrom) {
+ unsigned I = 1, E = CSI.size(), BeginI = 0;
+ for (; I < E;
@@ -0,0 +1,138 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec --ppc-enable-load-store-multiple < %s \
+; RUN: | FileCheck %s
+
+; CHECK: # %bb.0:# %entry
+; CHECK-NEXT: mflr
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/74415
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@@ -40,6 +40,12 @@ EnablePEVectorSpills("ppc-enable-pe-vector-spills",
cl::desc("Enable spills in prologue to vector
registers."),
cl::init(false), cl::Hidden);
+static cl::opt
+EnableLoadStoreMultiple("ppc-enable-load-store-multi
@@ -5723,7 +5723,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && (CM
@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation &C, const
JobAction &JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && C
https://github.com/chenzheng1030 approved this pull request.
Thanks for adding this. LGTM
https://github.com/llvm/llvm-project/pull/70255
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@@ -197,6 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///<
-fno-hip-fp32-correctly-rounde
CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is
enabled.
CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get
unique na
@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation &C, const
JobAction &JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && C
https://github.com/chenzheng1030 approved this pull request.
@ecnelises Let's first fix this for AIX. Could you please help to create a
github issue for the SPE? Thanks.
https://github.com/llvm/llvm-project/pull/70652
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@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128,
"V1LLLiULLiULLi", "", "vsx")
// Set the floating point rounding mode
BUILTIN(__builtin_setrnd, "di", "")
+// Barrier for instruction motion
chenzheng1030 wrote:
Can we add some comments here to
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/76495
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@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128,
"V1LLLiULLiULLi", "", "vsx")
// Set the floating point rounding mode
BUILTIN(__builtin_setrnd, "di", "")
+// Barrier for instruction motion
+BUILTIN(__builtin_ppc_fence, "v", "")
chenzheng1030 w
https://github.com/chenzheng1030 approved this pull request.
LGTM with nits.
https://github.com/llvm/llvm-project/pull/76495
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https://github.com/chenzheng1030 commented:
Maybe we can do some perf test between this expansion for set rounding mode and
the system library's version for `fesetround()`. On AIX, I saw some
improvements were introduced in the system library's implementation.
https://github.com/llvm/llvm-proj
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https://github.com/llvm/llvm-project/pull/67302
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@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
@@ -77,4 +77,196 @@ return: ; preds = %entry
ret i32 %retval3
}
-declare i32 @llvm.get.rounding() nounwind
+define void @setrnd_tozero() {
+; PPC32-LABEL: setrnd_tozero:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:mtfsb0 30
+; PPC32-NEXT:mtfsb1 3
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
Author: Chen Zheng
Date: 2022-04-20T05:14:22-04:00
New Revision: 3c776c70a76e9fe51fd978595315e6cef8e7fbb0
URL:
https://github.com/llvm/llvm-project/commit/3c776c70a76e9fe51fd978595315e6cef8e7fbb0
DIFF:
https://github.com/llvm/llvm-project/commit/3c776c70a76e9fe51fd978595315e6cef8e7fbb0.diff
LO
Author: Chen Zheng
Date: 2022-07-21T03:51:30-04:00
New Revision: ecdeabef385d13bc0c3b935cc56b09883fd7b108
URL:
https://github.com/llvm/llvm-project/commit/ecdeabef385d13bc0c3b935cc56b09883fd7b108
DIFF:
https://github.com/llvm/llvm-project/commit/ecdeabef385d13bc0c3b935cc56b09883fd7b108.diff
LO
@@ -24,13 +24,17 @@ void test_trap(void) {
__tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
+#ifdef __PPC64__
void test_builtin_ppc_rldimi() {
unsigned int shift;
unsigned long long mask;
unsigned long long res = __builti
@@ -5093,9 +5094,33 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
case PPC::BI__builtin_ppc_rlwnm:
return SemaValueIsRunOfOnes(TheCall, 2);
case PPC::BI__builtin_ppc_rlwimi:
- case PPC::BI__builtin_ppc_rldimi:
return SemaBuil
@@ -24,13 +24,17 @@ void test_trap(void) {
__tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
+#ifdef __PPC64__
void test_builtin_ppc_rldimi() {
unsigned int shift;
unsigned long long mask;
unsigned long long res = __builti
https://github.com/chenzheng1030 commented:
Looks almost good to me though I have a comment for the all one mask case.
https://github.com/llvm/llvm-project/pull/85040
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@@ -10764,30 +10764,53 @@ SDValue
PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getRegister(PPC::R2, MVT::i32);
case Intrinsic::ppc_rldimi: {
+assert(Subtarget.isPPC64() && "rldimi is only available in 64-bit!");
+if (Op.getConstantOperandVal
@@ -72,4 +72,74 @@ define i64 @rldimi_intrinsic(i64 %a) {
ret i64 %r3
}
+define i64 @rldimi5(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi5:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 4, 3, 8, 40
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rl
https://github.com/chenzheng1030 approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/85040
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@@ -10722,6 +10723,20 @@ static bool getVectorCompareInfo(SDValue Intrin, int
&CompareOpc,
return true;
}
+bool isContiguousMask(const APInt &Val, unsigned &MB, unsigned &ME,
chenzheng1030 wrote:
Is it possible to reuse `isRunOfOnes()`/`isRunOfOnes64()` in
@@ -641,6 +641,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine
&TM,
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ // setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
--
chenzheng1030 wrote:
> If you run into issues using normal integer ops, please file bugs. Most
> people aren't going to hand-tune their code like this; builtins like this are
> at best an ugly workaround.
Yes, a user should not try to write source code(using compiler builtins) to
just emit on
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+; CH
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/82968
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https://github.com/chenzheng1030 approved this pull request.
LGTM except two comments in the case change. One is a nit and the other one
should be other issue unrelated to this patch.
Thanks for implementing this.
https://github.com/llvm/llvm-project/pull/82968
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; N
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; N
@@ -1,70 +1,117 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 8
+; NOTE: Assertions have been autogenerated by u
chenzheng1030 wrote:
The failure in the buildkite should be unrelated. But would be better to double
confirm.
https://github.com/llvm/llvm-project/pull/82968
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@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; N
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+; CH
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/79109
>From 014b10f43e2d3f8564940e21033cee77c3c0c10e Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Tue, 23 Jan 2024 03:25:01 -0500
Subject: [PATCH 1/2] [PowerPC] Diagnose invalid combination with Altivec,
chenzheng1030 wrote:
Patch updated.
https://github.com/llvm/llvm-project/pull/79109
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chenzheng1030 wrote:
> I don't have any further comments, so I think LGTM.
Thanks Amy.
https://github.com/llvm/llvm-project/pull/79109
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https://github.com/chenzheng1030 closed
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https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/79109
Moved from https://reviews.llvm.org/D126302
The current behaviour with these three options is quite undesirable:
-mno-altivec -mvsx allows VSX to override no Altivec, thereby turning on both
-msoft-float -m
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool FullRegisterNames = false;
chenzheng1030 wrote:
Using a target feature bit for ass
Author: Chen Zheng
Date: 2021-05-12T23:00:52-04:00
New Revision: a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec
URL:
https://github.com/llvm/llvm-project/commit/a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec
DIFF:
https://github.com/llvm/llvm-project/commit/a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec.diff
LO
Author: Chen Zheng
Date: 2021-05-23T21:24:13-04:00
New Revision: 99d45ed22fd9c08ae81110956a817ac0eacded2e
URL:
https://github.com/llvm/llvm-project/commit/99d45ed22fd9c08ae81110956a817ac0eacded2e
DIFF:
https://github.com/llvm/llvm-project/commit/99d45ed22fd9c08ae81110956a817ac0eacded2e.diff
LO
Author: Chen Zheng
Date: 2021-06-16T03:17:56Z
New Revision: 4590b406c02e4e6803d2644195dbb78bc09c25c7
URL:
https://github.com/llvm/llvm-project/commit/4590b406c02e4e6803d2644195dbb78bc09c25c7
DIFF:
https://github.com/llvm/llvm-project/commit/4590b406c02e4e6803d2644195dbb78bc09c25c7.diff
LOG: [D
Author: Chen Zheng
Date: 2021-03-05T09:21:57-05:00
New Revision: afa76fe67a42f6d40d83a4f7d0cb03373045f3f4
URL:
https://github.com/llvm/llvm-project/commit/afa76fe67a42f6d40d83a4f7d0cb03373045f3f4
DIFF:
https://github.com/llvm/llvm-project/commit/afa76fe67a42f6d40d83a4f7d0cb03373045f3f4.diff
LO
Author: Chen Zheng
Date: 2022-12-25T21:01:02-05:00
New Revision: b1d7010caa4394e7f5b41c627702f6acabe0cec5
URL:
https://github.com/llvm/llvm-project/commit/b1d7010caa4394e7f5b41c627702f6acabe0cec5
DIFF:
https://github.com/llvm/llvm-project/commit/b1d7010caa4394e7f5b41c627702f6acabe0cec5.diff
LO
chenzheng1030 wrote:
> Is it possible that we fix the hack implementation with some future version
> (I will open an issue and work on it afterwards)? How about let's move on
> with current approach?
> @amy-kwan @stephenpeckham @bzEq @chenzheng1030 Appreciate your comments.
> Thank you!
I am
chenzheng1030 wrote:
The code formatting check fails.
https://github.com/llvm/llvm-project/pull/66316
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https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/68476
Extend `PPCTargetInfo::getGCCAddlRegNames()` to aix as well. The definition
should be common between Linux PPC and AIX PPC.
I also use "abi" as the ABI name for AIX ABI. This aligns with LLVM
PPCSubtarget
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/68476
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https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/68476
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/2] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/B
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs o
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | F
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
This is what I
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/68476
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https://github.com/chenzheng1030 approved this pull request.
Make sense to me. Thanks.
https://github.com/llvm/llvm-project/pull/68681
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@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
- else
-return TargetInfo::getGCCAddlRegNames();
+ return llvm::ArrayRef(G
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
FP and VMX reg
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/68476
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@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
@hubert-reinte
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/68476
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/3] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/B
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
Done.
https:/
https://github.com/chenzheng1030 closed
https://github.com/llvm/llvm-project/pull/68476
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@@ -833,6 +833,22 @@ TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
if (!Target->handleTargetFeatures(Opts->Features, Diags))
return nullptr;
+ // If TuneCPU is set, check if it contains all instruction sets needed by
+ // current feature map.
+ if (!Opts->Tun
Author: Chen Zheng
Date: 2023-04-14T06:24:57-04:00
New Revision: 4b0a25375e9006ef82cc51119ff223a28bb15646
URL:
https://github.com/llvm/llvm-project/commit/4b0a25375e9006ef82cc51119ff223a28bb15646
DIFF:
https://github.com/llvm/llvm-project/commit/4b0a25375e9006ef82cc51119ff223a28bb15646.diff
LO
Author: Chen Zheng
Date: 2023-06-04T21:37:48-04:00
New Revision: 4b27ad735c8da7cd21a7ea58614ebd4d3c940a89
URL:
https://github.com/llvm/llvm-project/commit/4b27ad735c8da7cd21a7ea58614ebd4d3c940a89
DIFF:
https://github.com/llvm/llvm-project/commit/4b27ad735c8da7cd21a7ea58614ebd4d3c940a89.diff
LO
Author: Chen Zheng
Date: 2023-06-05T04:00:26-04:00
New Revision: 225cf64e03b4e394c32e95fe1d6414e6e16be094
URL:
https://github.com/llvm/llvm-project/commit/225cf64e03b4e394c32e95fe1d6414e6e16be094
DIFF:
https://github.com/llvm/llvm-project/commit/225cf64e03b4e394c32e95fe1d6414e6e16be094.diff
LO
Author: Chen Zheng
Date: 2023-06-05T05:02:38-04:00
New Revision: b447dc5a4704bef8ced95495aa8d9ea477a26814
URL:
https://github.com/llvm/llvm-project/commit/b447dc5a4704bef8ced95495aa8d9ea477a26814
DIFF:
https://github.com/llvm/llvm-project/commit/b447dc5a4704bef8ced95495aa8d9ea477a26814.diff
LO
Author: Chen Zheng
Date: 2024-07-03T00:20:14-04:00
New Revision: 6a992bc89f5ca25d132abd044d78ecf27ae6e162
URL:
https://github.com/llvm/llvm-project/commit/6a992bc89f5ca25d132abd044d78ecf27ae6e162
DIFF:
https://github.com/llvm/llvm-project/commit/6a992bc89f5ca25d132abd044d78ecf27ae6e162.diff
LO
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/97541
For now only focus on the CPU type, will work on the CPU features part later.
With the CPU handling in TargetParser, clang and llc/opt are able to query
common interfaces.
So we can set same default CPU a
https://github.com/chenzheng1030 unassigned
https://github.com/llvm/llvm-project/pull/97541
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https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From 405639a8847111e401d5c2b69bb801c1c0ccadb7 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH] [PowerPC] add TargetParser for PPC target For now only focus
o
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From 405639a8847111e401d5c2b69bb801c1c0ccadb7 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH 1/2] [PowerPC] add TargetParser for PPC target For now only
foc
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/97541
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@@ -85,8 +85,59 @@
#define AIX_PPC9_VALUE 0x0002
#define AIX_PPC10_VALUE 0x0004
-// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on
Power7 and up on AIX.
// PPC_CPU(Name, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, AIXID)
+
+// Valid CPUs
https://github.com/chenzheng1030 commented:
Thanks for your comments @daltenty @ecnelises . Comments addressed.
https://github.com/llvm/llvm-project/pull/97541
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@@ -0,0 +1,120 @@
+//=== PPCTargetParser.cpp - Parser for target features --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1,52 +1,60 @@
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main(
chenzheng1030 wrote:
@efriedma-quic sorry to bother you. Do you think the new update is the correct
one? Thanks very much.
https://github.com/llvm/llvm-project/pull/93267
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https://github.com/chenzheng1030 closed
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https://github.com/chenzheng1030 closed
https://github.com/llvm/llvm-project/pull/106012
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https://github.com/chenzheng1030 commented:
Are there backend cases that shows with -disable-red-zone, the final assembly
is still correct?
https://github.com/llvm/llvm-project/pull/94581
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chenzheng1030 wrote:
> No. `-disable-red-zone` does nothing but add `noredzone` IR attribute to
> functions. We need to add cases to test for `noredzone` behavior on PPC (arm
> and x86 have).
Yeah, go ahead to add some backend tests first to make sure we have good
functionality for `noredzone
https://github.com/chenzheng1030 approved this pull request.
The small LIT cases seem all good. Based on that, the patch LGTM.
If possible, can you run some big applications with `-mno-redzone` to double
confirm the functionality? I am not so sure about its quality since the option
seems not b
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