[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

anil9 added inline comments. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:305 +// P10 Vector Centrifuge +BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "") nit : // P10 Vector Centrifuge built-in. Comment at: clang/include/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

anil9 added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:17 +unsigned int uia, *uiap; +signed int *ia; +signed short *sia; nit: It seems that most pull requests follow an ordering like first signed declaration and then unsigned, decla

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

anil9 added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:18 + // CHECK-NEXT: ret <4 x i32> + return vec_dive(vsia, vsib); +} I may be wrong but where are the variables declared ? I do not see the variables delclared above in the fil