@@ -271,22 +271,33 @@ namespace {
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
bool IsRetSmallStructInRegABI;
+ bool isComplexInRegABI;
+ // Size of GPR in bits
amy-kwan wrote:
```suggestion
bool IsComplexInRegABI;
// Size
@@ -2540,6 +2540,10 @@ def ffp_contract : Joined<["-"], "ffp-contract=">,
Group,
HelpText<"Form fused FP ops (e.g. FMAs)">,
Values<"fast,on,off,fast-honor-pragmas">;
+def fcomplex_ppc_gnu_abi : Flag<["-"], "fcomplex-ppc-gnu-abi">,
Group, Visibility<[ClangOption, CC1Optio
@@ -223,6 +223,8 @@ CODEGENOPT(MCDCCoverage , 1, 0) ///< Enable MC/DC code
coverage criteria.
/// If -fpcc-struct-return or -freg-struct-return is specified.
ENUM_CODEGENOPT(StructReturnConvention, StructReturnConventionKind, 2,
SRCK_Default)
+ /// If -fcomplex-ppc-gnu-ab
@@ -361,6 +439,9 @@ ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType
RetTy) const {
return ABIArgInfo::getDirect(CoerceTy);
}
}
+ if (isComplexInRegABI && RetTy->isAnyComplexType()) {
amy-kwan wrote:
Braces not needed here.
https://git
@@ -16560,32 +16560,69 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -16560,32 +16560,69 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP
https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/66316
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https://github.com/amy-kwan commented:
A question: For `PPCTLSDynamicCall.cpp`, would it be better if we instead
reworded some of the sentences and not use `Load*@toc`?
I thought about this for a bit and I think the full sentences may be a bit
better, so I added some sample comment suggestions
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -370,11 +370,22 @@ namespace llvm {
/// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
/// Op that combines two register copies of TOC entries
/// (region handle into R3 and variable offset into R4) followed by a
-/// GET_TLS_ADDR node which will be expanded to a cal
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -16560,32 +16560,69 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/82809
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@@ -132,6 +132,14 @@ PPC_LNX_CPU("power10",47)
#ifndef AIX_POWERPC_USE_SYS_CONF
#define AIX_POWERPC_USE_SYS_CONF
#define AIX_SYSCON_IMPL_IDX 1
+ #define AIX_SYSCON_CACHE_IDX 5
+ #define AIX_SYSCON_SMT_IDX 44
+ #define AIX_SYSCON_VMX_IDX 46
+ #define AIX_SYSCON_DFP_IDX
https://github.com/amy-kwan commented:
Group review comments.
https://github.com/llvm/llvm-project/pull/82809
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@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCp
@@ -16560,32 +16560,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCp
@@ -16560,32 +16560,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/66316
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@@ -145,9 +164,97 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
https://github.com/amy-kwan approved this pull request.
Thank you for the updates!
For me personally, I have no further comments. Unless if anyone else has any
comments, I think LGTM.
https://github.com/llvm/llvm-project/pull/66316
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@@ -139,6 +139,12 @@ class ModulePass;
/// and Local Exec models.
MO_TPREL_FLAG,
+/// MO_TLSLDM_FLAG - on AIX the ML relocation type is only valid for a
+/// reference to a TOC symbol from the symbol itself, and right now its
only
+/// user is the symbol "
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -835,6 +848,10 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
if (Flag == PPCII::MO_TLSGD_FLAG || Flag == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
return MCSymbolRefExpr::VariantKind::VK_PPC_AI
@@ -2835,6 +2862,10 @@ void PPCAIXAsmPrinter::emitInstruction(const
MachineInstr *MI) {
MMI->hasDebugInfo());
break;
}
+ case PPC::GETtlsMOD32AIX:
+ case PPC::GETtlsMOD64AIX:
+// A reference to .__tls_get_mod is unknown to the assembler so we need t
@@ -370,11 +370,23 @@ namespace llvm {
/// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
/// Op that combines two register copies of TOC entries
/// (region handle into R3 and variable offset into R4) followed by a
-/// GET_TLS_ADDR node which will be expanded to a cal
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -116,6 +116,10 @@ std::pair
PPCXCOFFObjectWriter::getRelocTypeAndSignSize(
return {XCOFF::RelocationType::R_TLS_IE, SignAndSizeForFKData};
case MCSymbolRefExpr::VK_PPC_AIX_TLSLE:
return {XCOFF::RelocationType::R_TLS_LE, SignAndSizeForFKData};
+case MCSym
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -3413,13 +3415,34 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
@@ -145,9 +164,89 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
https://github.com/amy-kwan commented:
Since this patch relies on the local-dynamic patch, I think the local-dynamic
changes are already in here, right? Do we know if there is a way yet to make
dependent pull requests, just so reviewing this patch may be a bit easier when
the local-dynamic cha
@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file
amy-kwan wrote:
```suggestion
// Definition of the following values are
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+
@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+#define AIX_SYSCON_IMPL_IDX
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+
@@ -362,8 +362,18 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// We support __builtin_cpu_supports/__builtin_cpu_is on targets that
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
+#define MINIMUM_AIX_OS_MAJOR 7
+#define MI
@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+#define AIX_SYSCON_IMPL_IDX
https://github.com/amy-kwan created
https://github.com/llvm/llvm-project/pull/79252
This patch disallows the use of the -maix-small-local-exec-tls and
-fno-data-sections options within clang, and also disallows the use of the
aix-small-local-exec-tls attribute with the -data-sections=false o
https://github.com/amy-kwan updated
https://github.com/llvm/llvm-project/pull/79252
>From 4999dba02844de0ea2fac843c06b08625bafe494 Mon Sep 17 00:00:00 2001
From: Amy Kwan
Date: Tue, 23 Jan 2024 22:19:49 -0600
Subject: [PATCH] [AIX][TLS] Disallow the use of -maix-small-local-exec-tls and
-fno-d
@@ -1,4 +1,7 @@
// RUN: not %clang_cc1 -triple powerpc64le-linux-gnu -emit-llvm %s -o -
long __attribute__((target("power8-vector,no-vsx"))) foo (void) { return 0; }
// expected-error {{option '-mpower8-vector' cannot be specified with
'-mno-vsx'}}
+long __attribute__((targ
https://github.com/amy-kwan approved this pull request.
I don't have any further comments, so I think LGTM.
https://github.com/llvm/llvm-project/pull/79109
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@@ -4,6 +4,9 @@
; RUN: < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED
; RUN: not llc -mtriple powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names \
; RUN: < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED
+; RUN: not llc -mtriple powerpc64-ibm-aix-x
https://github.com/amy-kwan updated
https://github.com/llvm/llvm-project/pull/79252
>From 87d6776702976983d0757390811c84142d345591 Mon Sep 17 00:00:00 2001
From: Amy Kwan
Date: Tue, 23 Jan 2024 22:19:49 -0600
Subject: [PATCH 1/2] [AIX][TLS] Disallow the use of -maix-small-local-exec-tls
and -f
https://github.com/amy-kwan updated
https://github.com/llvm/llvm-project/pull/79252
>From dc55bb565e6f778803604dfaa2874ce1d5fbdc86 Mon Sep 17 00:00:00 2001
From: Amy Kwan
Date: Tue, 23 Jan 2024 22:19:49 -0600
Subject: [PATCH 1/2] [AIX][TLS] Disallow the use of -maix-small-local-exec-tls
and -f
https://github.com/amy-kwan updated
https://github.com/llvm/llvm-project/pull/79252
>From 7e56809d82d1a1f64cee5f88607a0e279e56daca Mon Sep 17 00:00:00 2001
From: Amy Kwan
Date: Tue, 23 Jan 2024 22:19:49 -0600
Subject: [PATCH 1/2] [AIX][TLS] Disallow the use of -maix-small-local-exec-tls
and -f
https://github.com/amy-kwan updated
https://github.com/llvm/llvm-project/pull/79252
>From 3efadc26e156d8412972ce35cc52559295131eb8 Mon Sep 17 00:00:00 2001
From: Amy Kwan
Date: Tue, 23 Jan 2024 22:19:49 -0600
Subject: [PATCH 1/2] [AIX][TLS] Disallow the use of -maix-small-local-exec-tls
and -f
@@ -12,6 +15,10 @@ entry:
; Check that the aix-small-local-exec-tls attribute is not supported on Linux
and AIX (32-bit).
; CHECK-NOT-SUPPORTED: The aix-small-local-exec-tls attribute is only
supported on AIX in 64-bit mode.
+; Check that the aix-small-local-exec-tls attribu
@@ -124,10 +124,23 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU,
StringRef TuneCPU,
// Determine endianness.
IsLittleEndian = TM.isLittleEndian();
- if (HasAIXSmallLocalExecTLS && (!TargetTriple.isOSAIX() || !IsPPC64))
-report_fatal_error(
- "The ai
https://github.com/amy-kwan closed
https://github.com/llvm/llvm-project/pull/79252
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https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/68919
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@@ -1,11 +1,16 @@
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-X86
+// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | File
https://github.com/amy-kwan commented:
I think I primarily have minor nit comments. Thank you for the update, Nemanja.
https://github.com/llvm/llvm-project/pull/68919
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@@ -210,6 +210,15 @@ let TargetPrefix = "ppc" in { // All intrinsics start
with "llvm.ppc.".
[llvm_float_ty],
[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
[IntrNoMem]>;
+ // Load of a value provided by the system library
https://github.com/amy-kwan approved this pull request.
I meant to approve this before but forgot. I think LGTM once the comments are
addressed.
https://github.com/llvm/llvm-project/pull/68919
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ht
Author: Amy Kwan
Date: 2020-09-17T18:20:53-05:00
New Revision: 2c3bc918db35913437e9302b77b11c08eb3ea6e4
URL:
https://github.com/llvm/llvm-project/commit/2c3bc918db35913437e9302b77b11c08eb3ea6e4
DIFF:
https://github.com/llvm/llvm-project/commit/2c3bc918db35913437e9302b77b11c08eb3ea6e4.diff
LOG:
Author: Amy Kwan
Date: 2020-09-18T18:16:14-05:00
New Revision: 37e7673c21af1531b601ca975cb6118d04b6e1cc
URL:
https://github.com/llvm/llvm-project/commit/37e7673c21af1531b601ca975cb6118d04b6e1cc
DIFF:
https://github.com/llvm/llvm-project/commit/37e7673c21af1531b601ca975cb6118d04b6e1cc.diff
LOG:
Author: Amy Kwan
Date: 2020-09-22T11:31:44-05:00
New Revision: 079757b551f3ab5218af7344a7ab3c79976ec478
URL:
https://github.com/llvm/llvm-project/commit/079757b551f3ab5218af7344a7ab3c79976ec478
DIFF:
https://github.com/llvm/llvm-project/commit/079757b551f3ab5218af7344a7ab3c79976ec478.diff
LOG:
Author: Amy Kwan
Date: 2020-09-22T11:31:44-05:00
New Revision: b3147058dec7d42ae0284d6e6edf25eb762c8b89
URL:
https://github.com/llvm/llvm-project/commit/b3147058dec7d42ae0284d6e6edf25eb762c8b89
DIFF:
https://github.com/llvm/llvm-project/commit/b3147058dec7d42ae0284d6e6edf25eb762c8b89.diff
LOG:
Author: Amy Kwan
Date: 2020-09-23T22:55:25-05:00
New Revision: 6b136b19cbe4e96adea63b75f1f2f76ec25c708e
URL:
https://github.com/llvm/llvm-project/commit/6b136b19cbe4e96adea63b75f1f2f76ec25c708e
DIFF:
https://github.com/llvm/llvm-project/commit/6b136b19cbe4e96adea63b75f1f2f76ec25c708e.diff
LOG:
Author: Amy Kwan
Date: 2020-08-26T23:14:34-05:00
New Revision: 76b0f99ea854185c9866b0ab0f006137ba28e09e
URL:
https://github.com/llvm/llvm-project/commit/76b0f99ea854185c9866b0ab0f006137ba28e09e
DIFF:
https://github.com/llvm/llvm-project/commit/76b0f99ea854185c9866b0ab0f006137ba28e09e.diff
LOG:
Author: Amy Kwan
Date: 2020-09-01T17:16:43-05:00
New Revision: 0c2d872d5dec3eba10a8245bbcb3eebcf405ef9f
URL:
https://github.com/llvm/llvm-project/commit/0c2d872d5dec3eba10a8245bbcb3eebcf405ef9f
DIFF:
https://github.com/llvm/llvm-project/commit/0c2d872d5dec3eba10a8245bbcb3eebcf405ef9f.diff
LOG:
Author: Amy Kwan
Date: 2020-09-06T17:13:21-05:00
New Revision: efa57f9a7adb11a14b4e0d930f49070c769fa6ac
URL:
https://github.com/llvm/llvm-project/commit/efa57f9a7adb11a14b4e0d930f49070c769fa6ac
DIFF:
https://github.com/llvm/llvm-project/commit/efa57f9a7adb11a14b4e0d930f49070c769fa6ac.diff
LOG:
Author: Amy Kwan
Date: 2021-09-27T09:56:18-05:00
New Revision: 1f5b60ad47f1fa0493e4c9d8080eace56f87ee0c
URL:
https://github.com/llvm/llvm-project/commit/1f5b60ad47f1fa0493e4c9d8080eace56f87ee0c
DIFF:
https://github.com/llvm/llvm-project/commit/1f5b60ad47f1fa0493e4c9d8080eace56f87ee0c.diff
LOG:
Author: Amy Kwan
Date: 2021-07-30T09:35:43-05:00
New Revision: 5ea6117a9e9eae49ad1295fa422266ef3832e419
URL:
https://github.com/llvm/llvm-project/commit/5ea6117a9e9eae49ad1295fa422266ef3832e419
DIFF:
https://github.com/llvm/llvm-project/commit/5ea6117a9e9eae49ad1295fa422266ef3832e419.diff
LOG:
@@ -846,6 +872,17 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
if (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
+if (MO.getTarg
@@ -3412,13 +3414,28 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
@@ -145,9 +160,92 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -2710,6 +2758,15 @@ void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) {
MCSymbol *S = OutContext.getOrCreateSymbol(Name);
TCEntry = cast(
getObjFileLowering().getSectionForTOCEntry(S, TM));
+} else if (I.first.second ==
+ MCSymbolRefE
@@ -3281,6 +3288,9 @@ def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins
gprc:$offset, gprc:$handl
"#TLSGDAIX",
[(set i32:$rD,
(PPCTlsgdAIX i32:$offset, i32:$handle))]>;
+// This pseudo is expa
@@ -370,11 +370,23 @@ namespace llvm {
/// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
/// Op that combines two register copies of TOC entries
/// (region handle into R3 and variable offset into R4) followed by a
-/// GET_TLS_ADDR node which will be expanded to a cal
@@ -231,12 +231,18 @@ class PPCTargetAsmStreamer : public PPCTargetStreamer {
MCSymbolXCOFF *TCSym =
cast(Streamer.getCurrentSectionOnly())
->getQualNameSymbol();
- // On AIX, we have a region handle (symbol@m) and the variable offset
- /
@@ -145,9 +160,92 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -3412,13 +3414,28 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
amy-kwan wrote:
Also, is it intentional that we combined the patch to enable local-dynamic in
clang within this patch?
Just wondering since I thought I saw a separate patch for the clang portion
before (unless I am mistaken).
https://github.com/llvm/llvm-project/pull/66316
@@ -145,9 +163,88 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -6,6 +6,6 @@
#endif
static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
-static __thread int y __attribute((tls_model("local-dynamic"))); //
expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
+static __thread int y __attrib
@@ -145,9 +163,88 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -1622,6 +1629,9 @@ def TLSGDAIX8 :
"#TLSGDAIX8",
[(set i64:$rD,
(PPCTlsgdAIX i64:$offset, i64:$handle))]>;
+// This pseudo is expanded to load module-handle in X3, and the call to
GETtlsMOD64AIX.
-
@@ -145,9 +163,88 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -3412,13 +3416,23 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
@@ -145,9 +163,88 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +163,88 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -370,11 +370,23 @@ namespace llvm {
/// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
/// Op that combines two register copies of TOC entries
/// (region handle into R3 and variable offset into R4) followed by a
-/// GET_TLS_ADDR node which will be expanded to a cal
@@ -757,6 +772,17 @@ getTOCEntryTypeForMO(const MachineOperand &MO) {
llvm_unreachable("Unexpected operand type to get TOC type.");
}
}
+
+// FIXME: find alternative approach to get rid of this hack.
+// On AIX, TLS-local-dynamic requires that the symbol for the module ha
Author: Amy Kwan
Date: 2023-09-07T20:05:29-05:00
New Revision: b1922e55ab3b35dff99238fd0b74be00df0472e7
URL:
https://github.com/llvm/llvm-project/commit/b1922e55ab3b35dff99238fd0b74be00df0472e7
DIFF:
https://github.com/llvm/llvm-project/commit/b1922e55ab3b35dff99238fd0b74be00df0472e7.diff
LOG:
Author: Amy Kwan
Date: 2023-06-19T12:17:30-05:00
New Revision: 706b5472d897ca75ebd210e4109637793288bcf2
URL:
https://github.com/llvm/llvm-project/commit/706b5472d897ca75ebd210e4109637793288bcf2
DIFF:
https://github.com/llvm/llvm-project/commit/706b5472d897ca75ebd210e4109637793288bcf2.diff
LOG:
Author: Amy Kwan
Date: 2023-05-24T12:29:23-05:00
New Revision: 61262f9ef4194963c3231932e39f11d89cf80a12
URL:
https://github.com/llvm/llvm-project/commit/61262f9ef4194963c3231932e39f11d89cf80a12
DIFF:
https://github.com/llvm/llvm-project/commit/61262f9ef4194963c3231932e39f11d89cf80a12.diff
LOG:
Author: Amy Kwan
Date: 2023-05-15T12:18:06-05:00
New Revision: 2239fd50bd807ce32c54e03d548cc0cc7c6e64dd
URL:
https://github.com/llvm/llvm-project/commit/2239fd50bd807ce32c54e03d548cc0cc7c6e64dd
DIFF:
https://github.com/llvm/llvm-project/commit/2239fd50bd807ce32c54e03d548cc0cc7c6e64dd.diff
LOG:
https://github.com/amy-kwan commented:
Some initial comments for now.
https://github.com/llvm/llvm-project/pull/80069
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https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/80069
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@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error<
def err_builtin_target_unsupported : Error<
"builtin is not supported on this target">;
+def err_builtin_aix_os_unsupported : Error<
+ "this builtin is available only on AIX 7.2 and later operating syst
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