[llvm] [clang] [AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (PR #79614)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/79614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [FMV] Change feature priorities according to ACLE. (PR #79316)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/79316 >From d0dfa97f58a183d7fab1e6ddf2ef29ba3b3c3f36 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Wed, 24 Jan 2024 15:26:01 + Subject: [PATCH] [FMV] Change feature priorities according to ACLE. This

[clang] [llvm] [AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (PR #79614)

https://github.com/labrinea milestoned https://github.com/llvm/llvm-project/pull/79614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (PR #79614)

labrinea wrote: /cherry-pick ae8005f https://github.com/llvm/llvm-project/pull/79614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [FMV] Change feature priorities according to ACLE. (PR #79316)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/79316 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [FMV] Change feature priorities according to ACLE. (PR #79316)

@@ -659,21 +659,21 @@ int hoo(void) { // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsimdMfp16fml // CHECK-SAME: () #[[ATTR7]] { // CHECK-NEXT: entry: // CH

[compiler-rt] [clang] [llvm] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

https://github.com/labrinea created https://github.com/llvm/llvm-project/pull/78788 The patch adds support for FEAT_MOPS (Memory Copy and Memory Set instructions) in Function Multi Versioning. The bits [19:16] of the system register ID_AA64ISAR2_EL1 indicate whether FEAT_MOPS is implemented in

[clang] [compiler-rt] [llvm] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/78788 >From 3c696fa3c4f5459ace01faffab0eb028f3b6f4eb Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Fri, 19 Jan 2024 21:07:46 + Subject: [PATCH] [AArch64][FMV] Support feature MOPS in Function Multi V

[clang] [compiler-rt] [llvm] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

@@ -172,6 +172,11 @@ static void __init_cpu_features_constructor(unsigned long hwcap, // ID_AA64ISAR1_EL1.LS64 >= 0b0011 if (extractBits(ftr, 60, 4) >= 0x3) setCPUFeature(FEAT_LS64_ACCDATA); + labrinea wrote: Done https://github.com/llvm/llvm-p

[clang] [compiler-rt] [llvm] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

https://github.com/labrinea edited https://github.com/llvm/llvm-project/pull/78788 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[compiler-rt] [llvm] [clang] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/78788 >From 425bf555fcc2c2ca2fca72822618702ac9278be6 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Fri, 19 Jan 2024 21:07:46 + Subject: [PATCH] [AArch64][FMV] Support feature MOPS in Function Multi V

[compiler-rt] [llvm] [clang] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/78788 >From 4f639d0ca7edc5a1e8369e6ebec10458e0836948 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Fri, 19 Jan 2024 21:07:46 + Subject: [PATCH] [AArch64][FMV] Support feature MOPS in Function Multi V

[compiler-rt] [clang] [llvm] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/78788 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 1bd5ea9 - [ARM] Mitigate the cve-2021-35465 security vulnurability.

Author: Alexandros Lamprineas Date: 2021-09-16T12:56:43+01:00 New Revision: 1bd5ea968e9262a09512a64bca1624818640bc5b URL: https://github.com/llvm/llvm-project/commit/1bd5ea968e9262a09512a64bca1624818640bc5b DIFF: https://github.com/llvm/llvm-project/commit/1bd5ea968e9262a09512a64bca1624818640bc

[clang] 29b263a - [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'

Author: Alexandros Lamprineas Date: 2021-07-31T09:51:28+01:00 New Revision: 29b263a34f1afbae9c95bf48eab7e8aac8132a80 URL: https://github.com/llvm/llvm-project/commit/29b263a34f1afbae9c95bf48eab7e8aac8132a80 DIFF: https://github.com/llvm/llvm-project/commit/29b263a34f1afbae9c95bf48eab7e8aac8132a

[clang] 8689f5e - [AArch64] Add support for the 'R' architecture profile.

Author: Alexandros Lamprineas Date: 2021-10-27T12:32:30+01:00 New Revision: 8689f5e6e77394528155b624d74557790278a407 URL: https://github.com/llvm/llvm-project/commit/8689f5e6e77394528155b624d74557790278a407 DIFF: https://github.com/llvm/llvm-project/commit/8689f5e6e77394528155b624d74557790278a4

[PATCH] D26968: [ARM] Add Driver support for emmitting the missing Tag_ABI_enum_size build attribute values

labrinea created this revision. labrinea added reviewers: cfe-commits, rengolin. Herald added a subscriber: aemerson. The ABI for the ARM architecture describes four build attribute values for the size of enumer

[PATCH] D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:5407 + Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", + Opts.ShortEnums || Opts.ABIEnums ? "1" : "4"); rengolin wrote: > Isn't ABIEnums 4? Shouldn't this be: > >

[PATCH] D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values

labrinea added a comment. Your suggestion that if all four options are mutually exclusive, then they should be a single integer option, totally makes sense to me. We could use a single integer option and make the old boolean flags deprecated (i.e. map '-fshort-enums' and 'fno-short enums' to th

[PATCH] D12722: cortex-r5f and cortex-m4f are unknown names for clang

labrinea created this revision. labrinea added reviewers: rengolin, richard.barton.arm. labrinea added a subscriber: cfe-commits. Tests are currently passing but warning messages are suppressed. http://reviews.llvm.org/D12722 Files: test/CodeGen/arm-target-features.c Index: test/CodeGen/arm-t

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added a comment. Ping http://reviews.llvm.org/D12633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

r247138 - [ARM] "cortex-r5f" and "cortex-m4f" are unknown names for clang.

Author: alelab01 Date: Wed Sep 9 06:29:06 2015 New Revision: 247138 URL: http://llvm.org/viewvc/llvm-project?rev=247138&view=rev Log: [ARM] "cortex-r5f" and "cortex-m4f" are unknown names for clang. The tests in test/CodeGen/arm-target-features.c are currently passing but warning messages are sup

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4785 @@ +4784,3 @@ +if (Opts.C99 && !Opts.Freestanding) { + Builder.defineMacro("__ARM_FP_FENV_ROUNDING", "1"); + Builder.defineMacro("__STDC_IEC_559__", "1"); rengolin wrote: > I'm no

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea updated this revision to Diff 35223. labrinea added a comment. Patch updated. http://reviews.llvm.org/D12633 Files: lib/Basic/Targets.cpp test/Preprocessor/aarch64-target-features.c test/Preprocessor/arm-target-features.c Index: test/Preprocessor/arm-target-features.c ==

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added a comment. @rsmith @t.p.northover could you please give us some feedback on this? Thanks. http://reviews.llvm.org/D12633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commit

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added a comment. GCC online docs state: > -ffast-math > Might allow some programs designed to not be too dependent on IEEE behavior > for floating-point to run faster, or die trying. Sets > -funsafe-math-optimizat

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea updated this revision to Diff 35628. labrinea added a comment. @t.p.northover I think we should not be defining _ARM_FP_FENV_ROUNDING on neither of ARM and AArch64 targets since "-frounding-math" is not available on clang: clang/llvm don't support C99 FP rounding mode pragmas (FENV_ACCE

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added inline comments. Comment at: lib/Frontend/CompilerInvocation.cpp:1711 @@ -1710,1 +1710,3 @@ Args.hasArg(OPT_cl_fast_relaxed_math); + Opts.UnsafeFPMath = Args.hasArg(OPT_menable_unsafe_fp_math) || + Args.hasArg(OPT_cl_unsafe_math_optimiza

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added a comment. In http://reviews.llvm.org/D12633#252758, @labrinea wrote: > @t.p.northover I think we should not be defining _ARM_FP_FENV_ROUNDING on > neither of ARM and AArch64 targets since "-frounding-math" is not available > on clang: clang/llvm don't support C99 FP rounding mod

[PATCH] D13217: The Driver does not set the +strict-align flag when targeting armv6m + netbsd

labrinea created this revision. labrinea added reviewers: cfe-commits, rengolin. Herald added subscribers: rengolin, aemerson. Tests are misssing for armv6m + darwin as well. http://reviews.llvm.org/D13217 Files: lib/Basic/Targets.cpp lib/Driver/Tools.cpp test/Driver/arm-alignment.c Index

Re: [PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea added a comment. ping http://reviews.llvm.org/D12633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

r249140 - Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets.

Author: alelab01 Date: Fri Oct 2 09:56:37 2015 New Revision: 249140 URL: http://llvm.org/viewvc/llvm-project?rev=249140&view=rev Log: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets. Differential Revision: http://reviews.llvm.org/D12633 Modified: cfe/trunk

Re: [PATCH] D13217: [ARM] The Driver does not set the +strict-align flag when targeting armv6m + netbsd

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4456 @@ -4455,3 +4455,1 @@ -if (ArchVersion < 6 || - (ArchVersion == 6 && ArchProfile == llvm::ARM::PK_M)) rengolin wrote: > Why is this not necessary any more? The logic is still nece

Re: [PATCH] D13217: [ARM] The Driver does not set the +strict-align flag when targeting armv6m + netbsd

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4456 @@ -4455,3 +4455,1 @@ -if (ArchVersion < 6 || - (ArchVersion == 6 && ArchProfile == llvm::ARM::PK_M)) rengolin wrote: > labrinea wrote: > > rengolin wrote: > > > Why is this not n

r249308 - The Driver does not set the +strict-align flag when targeting

Author: alelab01 Date: Mon Oct 5 07:45:10 2015 New Revision: 249308 URL: http://llvm.org/viewvc/llvm-project?rev=249308&view=rev Log: The Driver does not set the +strict-align flag when targeting [ARM] armv6m + netbsd. Tests are misssing for armv6m + darwin as well. Differential Revision: http:/

[PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea created this revision. labrinea added subscribers: cfe-commits, llvm-commits. Herald added subscribers: rengolin, aemerson. Implementation and testing of ACLE 2.0 macros, for details see the above document: [[ http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.p

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea updated this revision to Diff 32934. labrinea added a comment. Reordered macro definitions to make review easier. http://reviews.llvm.org/D12244 Files: lib/Basic/Targets.cpp test/Preprocessor/aarch64-target-features.c test/Preprocessor/arm-acle-6.4.c test/Preprocessor/arm-acle-

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4757 @@ -4679,2 +4756,3 @@ Builder.defineMacro("__ARM_NEON__"); + Builder.defineMacro("__ARM_NEON_FP", "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); } According to the ACLE document,

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4685-4686 @@ +4684,4 @@ +// ACLE 6.5.2 Half-precision (16-bit) floating-point format +if (HW_FP & HW_FP_HP) + Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); + olista01 wrote: > The

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4685-4686 @@ +4684,4 @@ +// ACLE 6.5.2 Half-precision (16-bit) floating-point format +if (HW_FP & HW_FP_HP) + Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); + olista01 wrote: > lab

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea updated this revision to Diff 33054. labrinea added a comment. _ARM_FP16_FORMAT_IEEE and _ARM_FP16_ARGS should be defined unconditionally. When hardware does not support them library calls are emitted. http://reviews.llvm.org/D12244 Files: lib/Basic/Targets.cpp test/Preprocessor/a

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea added a comment. Could I have some feedback please? http://reviews.llvm.org/D12244 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea added inline comments. Comment at: lib/Basic/Targets.cpp:4790 @@ +4789,3 @@ + Builder.defineMacro("__ARM_FEATURE_SAT", "1"); + Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); +} rengolin wrote: > Isn't there a combination where you'll emit t

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea added a comment. This means accepted? http://reviews.llvm.org/D12244 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

r246768 - Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets.

Author: alelab01 Date: Thu Sep 3 09:40:57 2015 New Revision: 246768 URL: http://llvm.org/viewvc/llvm-project?rev=246768&view=rev Log: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets. Differential Revision: http://reviews.llvm.org/D12244 Change-Id: Iffd4e822c15e

[PATCH] D12633: Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] targets

labrinea created this revision. labrinea added reviewers: rengolin, richard.barton.arm. labrinea added a subscriber: cfe-commits. Herald added subscribers: rengolin, aemerson. Added the remaining macros and corresponding regression tests. http://reviews.llvm.org/D12633 Files: lib/Basic/Targets

r246946 - Refactoring of how ARMTargetInfo handles default target features.

Author: alelab01 Date: Sun Sep 6 11:15:45 2015 New Revision: 246946 URL: http://llvm.org/viewvc/llvm-project?rev=246946&view=rev Log: Refactoring of how ARMTargetInfo handles default target features. Differential Revision: http://reviews.llvm.org/D11299 Modified: cfe/trunk/lib/Basic/Targets

Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

labrinea closed this revision. labrinea added a comment. committed as r246768 http://reviews.llvm.org/D12244 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea created this revision. labrinea added reviewers: rengolin, cfe-commits, bsmith. Herald added subscribers: rengolin, aemerson. When running clang with an arm triple such as '--target=thumbv7m-arm-none-eabi' that has a thumb only CPU by default (cortex-m3), and when using the assembler, t

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea updated this revision to Diff 38552. http://reviews.llvm.org/D14121 Files: lib/Driver/ToolChain.cpp test/Driver/arm-ias-Wa.s Index: test/Driver/arm-ias-Wa.s === --- test/Driver/arm-ias-Wa.s +++ test/Driver/arm-ias-Wa.s

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea added inline comments. Comment at: lib/Driver/ToolChain.cpp:485 @@ +484,3 @@ +if ((ARM::parseArchProfile(Suffix) == ARM::PK_M) || +(InputType != types::TY_PP_Asm && + Args.hasFlag(options::OPT_mthumb, options::OPT_mno_thumb, ThumbDefault))) --

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea updated this revision to Diff 38558. http://reviews.llvm.org/D14121 Files: lib/Driver/ToolChain.cpp lib/Driver/Tools.cpp test/Driver/arm-ias-Wa.s Index: test/Driver/arm-ias-Wa.s === --- test/Driver/arm-ias-Wa.s +++ te

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea added a comment. It seems I missed your comments before updating the patch. @t.p.northover: What is the exact command? "clang -arch armv7 -c tmp.s" didn't work for me. http://reviews.llvm.org/D14121 ___ cfe-commits mailing list cfe-commits

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea added a comment. Is this revision valid after all? I am confused by Tim's comment. I did not see any regressions locally. Comment at: lib/Driver/ToolChain.cpp:472 @@ -471,2 +471,3 @@ +bool ThumbDefault = (ARM::parseArchProfile(Suffix) == ARM::PK_M) || (Suffi

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea added a comment. In http://reviews.llvm.org/D14121#276389, @t.p.northover wrote: > If you're on Linux or something you need "clang -target x86_64-apple-darwin > -arch armv7 -c tmp.s". Another mess I keep meaning to fix. > > I suspect the reason for this hack is that we've already change

Re: [PATCH] D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as

labrinea updated this revision to Diff 38633. labrinea added a comment. I think the patch is now in it's final shape: - kept TY_PP_Asm check - added darwin and armv7m in checks in tests - cached IsMProfile - used ARM::parseArchVersion http://reviews.llvm.org/D14121 Files: lib/Driver/ToolChai

r251507 - When running clang with an arm triple such as '--target=thumbv7m-none-eabi'

Author: alelab01 Date: Wed Oct 28 05:10:03 2015 New Revision: 251507 URL: http://llvm.org/viewvc/llvm-project?rev=251507&view=rev Log: When running clang with an arm triple such as '--target=thumbv7m-none-eabi' that has a thumb only CPU by default (cortex-m3), and when using the assembler, the def

[PATCH] D14384: [ARM] Clang gives unintended warning message for 'mthumb' + M-profiles

labrinea created this revision. labrinea added reviewers: cfe-commits, rengolin. Herald added subscribers: rengolin, aemerson. ``` $ clang --target=armv7m-none-eabi -mthumb -march=armv7-m -c test.c clang-3.8: warning: argument unused during compilation: '-mthumb' ``` http://reviews.llvm.org/D1438

r252175 - [ARM] Clang gives unintended warning message for 'mthumb' + M-profiles:

Author: alelab01 Date: Thu Nov 5 11:11:55 2015 New Revision: 252175 URL: http://llvm.org/viewvc/llvm-project?rev=252175&view=rev Log: [ARM] Clang gives unintended warning message for 'mthumb' + M-profiles: $ clang --target=armv7m-none-eabi -mthumb -march=armv7-m -c test.c clang-3.8: warning: arg

r263245 - Add tests for ARM Cortex-R8

Author: alelab01 Date: Fri Mar 11 09:03:40 2016 New Revision: 263245 URL: http://llvm.org/viewvc/llvm-project?rev=263245&view=rev Log: Add tests for ARM Cortex-R8 Add command-line tests for ARM Cortex-R8 checking that the driver calls clang -cc1 with the correct little-endian/big-endian, and ARM/

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

labrinea updated the summary for this revision. labrinea updated this revision to Diff 43885. labrinea added a comment. Disabled optimizers. http://reviews.llvm.org/D15223 Files: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c test/CodeGen/arm-v8.1a-neon-intrinsics.c Index: test/CodeGen/arm-v

r256822 - [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

Author: alelab01 Date: Tue Jan 5 03:58:29 2016 New Revision: 256822 URL: http://llvm.org/viewvc/llvm-project?rev=256822&view=rev Log: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics. Differential Revision: http://reviews.llvm.org/D15223 Modified: cfe/trunk/test/Code

[PATCH] D14982: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract.

labrinea created this revision. labrinea added reviewers: jmolloy, rengolin, cfe-commits. Herald added subscribers: rengolin, aemerson. The following instructions are added to AArch32 instruction set: - VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Retu ing High Half - V

Re: [PATCH] D14982: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract.

labrinea updated this revision to Diff 41316. labrinea added a comment. @t.p.northover you were right, my patch was missing predefined guard macros for the instrinsics. I've now updated the patch. http://reviews.llvm.org/D14982 Files: include/clang/Basic/arm_neon.td lib/Basic/Targets.cpp

r254250 - ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply

Author: alelab01 Date: Sun Nov 29 04:43:59 2015 New Revision: 254250 URL: http://llvm.org/viewvc/llvm-project?rev=254250&view=rev Log: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract. The following instructions are added to AArch32 instruction set: - VQRDMLAH:

r254251 - ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply

Author: alelab01 Date: Sun Nov 29 04:53:28 2015 New Revision: 254251 URL: http://llvm.org/viewvc/llvm-project?rev=254251&view=rev Log: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract. Add missing tests that accidentally were not committed in rL254250. Differen

[PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

labrinea created this revision. labrinea added reviewers: jmolloy, rengolin, echristo, cfe-commits. Herald added subscribers: rengolin, aemerson. Existing tests are currently testing generated backend assembly. We want to test the generated frontend IR as well. As discussed on the list we would l

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

labrinea updated this revision to Diff 42035. labrinea added a comment. ASM tests have been removed. http://reviews.llvm.org/D15223 Files: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c test/CodeGen/arm-v8.1a-neon-intrinsics.c Index: test/CodeGen/arm-v8.1a-neon-intrinsics.c =

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

labrinea added inline comments. Comment at: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c:4 @@ -3,4 +3,3 @@ // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +v8.1a -O3 -S -o - %s \ -// RUN: | FileCheck %s --check-prefix=CHECK --check-

RE: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

Ping. http://reviews.llvm.org/D15223 -Original Message- From: Eric Christopher [mailto:echri...@gmail.com] Sent: 07 December 2015 19:18 To: Alexandros Lamprineas; James Molloy; renato.go...@linaro.org; cfe-commits@lists.llvm.org Cc: Amara Emerson Subject: Re: [PATCH] D15223: [ARM] [AARC

Re: [PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

labrinea added a comment. Hi Eric, The main optimization I feel is useful is mem2reg. Without that, if I want to properly check the right values go to the right operands of the intrinsic calls I have to write FileCheck matchers that match stores and their relevant loads, plus bitcasts. This no

[clang] [clang] Refactor target attribute mangling. (PR #81893)

https://github.com/labrinea created https://github.com/llvm/llvm-project/pull/81893 Before this patch all of the 'target', 'target_version' and 'target_clones' attributes were sharing a common mangling logic across different targets. However we would like to differenciate this logic, therefore

[clang] [clang] Refactor target attribute mangling. (PR #81893)

labrinea wrote: > > I wonder if this should be a part of the Targets in CodeGen instead of here? > > Hrm, this is a bad idea as the rest of mangling is in AST, but having > mangling outside of AST seems to be the problem here. I could move the logic under ABIInfo which is already referencing A

[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/96628 >From ff4635208e9cd83c6735c95ebf12125ca737029a Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Tue, 25 Jun 2024 00:27:45 +0100 Subject: [PATCH 1/3] [clang][FMV] Do not omit explicit default target_ver

[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/96628 >From ff4635208e9cd83c6735c95ebf12125ca737029a Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Tue, 25 Jun 2024 00:27:45 +0100 Subject: [PATCH 1/3] [clang][FMV] Do not omit explicit default target_ver

[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/96628 >From ff4635208e9cd83c6735c95ebf12125ca737029a Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Tue, 25 Jun 2024 00:27:45 +0100 Subject: [PATCH 1/3] [clang][FMV] Do not omit explicit default target_ver

[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/96628 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

https://github.com/labrinea edited https://github.com/llvm/llvm-project/pull/97761 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

https://github.com/labrinea edited https://github.com/llvm/llvm-project/pull/97761 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

@@ -59,15 +59,22 @@ int bar() { return m.goo(1) + foo(1) + foo(); } +// Example to demonstrate that at the point of use we haven't yet seen the default. +// At that point a declaration for the unmangled symbol is emitted, which is later +// replaced by the ifunc symbol (on

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

@@ -261,9 +261,9 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void // CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,-v9.5a" } // CHECK: attribute

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

@@ -11,7 +11,7 @@ int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; } int __attribute__((target_version("crc+ls64_v"))) fmv(void) { return 7; } int __attribute__((target_version("bti"))) fmv(void) { return 8; } int __attribute__((target_version("sme2"))) fmv(

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

@@ -59,15 +59,22 @@ int bar() { return m.goo(1) + foo(1) + foo(); } +// Example to demonstrate that at the point of use we haven't yet seen the default. +// At that point a declaration for the unmangled symbol is emitted, which is later +// replaced by the ifunc symbol (on

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

@@ -4210,9 +4192,7 @@ void CodeGenModule::emitMultiVersionFunctions() { return cast(Func); }; -bool HasDefaultDecl = !FD->isTargetVersionMultiVersion(); -bool ShouldEmitResolver = -!getContext().getTargetInfo().getTriple().isAArch64(); +bool Shoul

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

@@ -4224,10 +4204,8 @@ void CodeGenModule::emitMultiVersionFunctions() { llvm::Function *Func = createFunction(CurFD); Options.emplace_back(Func, TA->getArchitecture(), Feats); } else if (const auto *TVA = CurFD->getAttr()) { -bool

[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)

labrinea wrote: > It's really hard to tell what is changing here because the existing tests are > so non-specific. I appreciate that. The tests would benefit from some tidying up, we should prioritize this at some point. In case it helps most of the test changes are due to symbols being gener

[clang] [llvm] [AArch64] Split FeatureLS64 to LS64_ACCDATA and LS64_V. (PR #101712)

labrinea wrote: I am abandoning this PR in favor of https://github.com/ARM-software/acle/pull/346 https://github.com/llvm/llvm-project/pull/101712 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/

[clang] [llvm] [AArch64] Split FeatureLS64 to LS64_ACCDATA and LS64_V. (PR #101712)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/101712 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [ARM][AArch64] Split FEAT_SHA1 from FEAT_SHA256. (PR #99816)

labrinea wrote: I am abandoning this PR in favor of https://github.com/ARM-software/acle/pull/346 https://github.com/llvm/llvm-project/pull/99816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/c

[clang] [llvm] [ARM][AArch64] Split FEAT_SHA1 from FEAT_SHA256. (PR #99816)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/99816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [FMV][AArch64] Unify ls64, ls64_v and ls64_accdata. (PR #108024)

https://github.com/labrinea created https://github.com/llvm/llvm-project/pull/108024 Originally I tried spliting these features in the compiler with https://github.com/llvm/llvm-project/pull/101712, but I realized that there's no way to preserve backwards compatibility, therefore we decided to

[clang] [clang][FMV] Pass the '+fmv' target-feature when FMV is enabled. (PR #87942)

https://github.com/labrinea created https://github.com/llvm/llvm-project/pull/87942 This will allow the backend to enable the corresponding subtarget feature (FeatureFMV), which in turn can be queried for llvm codegen decisions. See #87939 for example. >From 38eea2eca0a852965f6b3d2037c5c0f290

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/94279 >From a413428bb0fdcd45b4a251e385b6cc00ff6a0a2c Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 3 Jun 2024 19:57:49 +0100 Subject: [PATCH 1/2] [AArch64] Decouple feature dependency expansion. The

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/94279 >From a413428bb0fdcd45b4a251e385b6cc00ff6a0a2c Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 3 Jun 2024 19:57:49 +0100 Subject: [PATCH 1/3] [AArch64] Decouple feature dependency expansion. The

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/94279 >From a413428bb0fdcd45b4a251e385b6cc00ff6a0a2c Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 3 Jun 2024 19:57:49 +0100 Subject: [PATCH 1/4] [AArch64] Decouple feature dependency expansion. The

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

@@ -1110,23 +1071,26 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { bool FoundArch = false; auto SplitAndAddFeatures = [](StringRef FeatString, -std::vector &Features) { +s

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

https://github.com/labrinea edited https://github.com/llvm/llvm-project/pull/94279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

labrinea wrote: > Not supporting "neon" as a name would seem like a mistake if it was removed, > but I don't believe this patch does that. It does https://github.com/llvm/llvm-project/pull/94279 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/94279 >From a413428bb0fdcd45b4a251e385b6cc00ff6a0a2c Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 3 Jun 2024 19:57:49 +0100 Subject: [PATCH 1/4] [AArch64] Decouple feature dependency expansion. The

[clang] [llvm] [AArch64] Decouple feature dependency expansion. (PR #94279)

https://github.com/labrinea closed https://github.com/llvm/llvm-project/pull/94279 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

<    1   2   3   4   5   6   >