@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
KanRobert wrote:
Drop -show-mc-encoding
ht
@@ -54,6 +55,14 @@
using namespace llvm;
+static cl::opt EnableBranchHint("branch-hint",
KanRobert wrote:
`enable-branch-hint` is more in line with our current naming habits
https://github.com/llvm/llvm-project/pull/97721
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KanRobert wrote:
This test is too verbose, not robust and miss coverage. I would suggest the
following
```
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64 -mattr=+branch-hint
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KanRobert wrote:
Updated.
https://github.com/llvm/llvm-project/pull/97721
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LGTM
https://github.com/llvm/llvm-project/pull/97721
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KanRobert wrote:
> I suppose the name of relocation used by binutils is
> R_X86_64_CODE_4_GOTPCRELX Also binutils has added
> R_X86_64_CODE_5_GOTPCRELX/R_X86_64_CODE_6_GOTPCRELX, for evex relocation
> Refer to
> [bminor/binutils-gdb@3d5a60d](https://github.com/bminor/binutils-gdb/commit/3d5a6
https://github.com/KanRobert approved this pull request.
LGTM, but please put the link for the discussion in GCC community in description
https://github.com/llvm/llvm-project/pull/103898
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@@ -954,6 +954,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__CCMP__");
if (HasCF)
Builder.defineMacro("__CF__");
+ if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
KanRobert wrote:
Add comment
`Condition
https://github.com/KanRobert approved this pull request.
LGTM with a suggestion
https://github.com/llvm/llvm-project/pull/88343
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LGTM
https://github.com/llvm/llvm-project/pull/95890
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Author: Shengchen Kan
Date: 2024-05-29T17:34:26+08:00
New Revision: 0f7b4b04a548e10d0f552f13bebc21972d55d7f6
URL:
https://github.com/llvm/llvm-project/commit/0f7b4b04a548e10d0f552f13bebc21972d55d7f6
DIFF:
https://github.com/llvm/llvm-project/commit/0f7b4b04a548e10d0f552f13bebc21972d55d7f6.diff
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
+
KanRobert wrote:
Remove this test and update llvm/test/CodeGen/X86/apx/asm-constraint.ll
https://github.com/llvm/llvm-project/pull/92338
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KanRobert wrote:
Merge this into llvm/test/CodeGen/X86/apx/inline-asm-jr-constraint.ll
You can add `not` at each run line. llc does not stop processing when
encountering such kind of error.
https://github.com/llvm/llvm-project/pull/92338
_
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return std::m
KanRobert wrote:
Nits: Rename this file to llvm/test/CodeGen/X86/apx/asm-constraint-jR.ll to
align with existing one
https://github.com/llvm/llvm-project/pull/92338
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KanRobert wrote:
Nits: Rename this file to llvm/test/CodeGen/X86/apx/asm-constraint-jr.ll to
align with existing one
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@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
KanRobert wrote:
You can use sth like
```
not llc
https://github.com/KanRobert edited
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/KanRobert commented:
Update the tests for `m512_maskz_cvt_roundepu64_ps` e.t.c (in
avx512dq-builtins.c )?
https://github.com/llvm/llvm-project/pull/99691
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@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
@@ -248,6 +248,10 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
}
+ llvm::StringSet<> SubFeaturesOfAPX = {"egpr", "push2pop2", "ppx", "ndd",
+
@@ -266,13 +270,24 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
bool IsNegative = Name.starts_with("no-");
+
+bool Not64Bit = ArchType != llvm::Triple::x86_64;
KanRobert wrote:
It would not. We check the option
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/101151
>From 650f29dd40714ebe52bf5d0a407bd45b9d248269 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 30 Jul 2024 16:26:39 +0800
Subject: [PATCH 1/4] [Driver,CodeGen] Report error when enabling 64-bit-only
f
@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/101151
>From 650f29dd40714ebe52bf5d0a407bd45b9d248269 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 30 Jul 2024 16:26:39 +0800
Subject: [PATCH 1/5] [Driver,CodeGen] Report error when enabling 64-bit-only
f
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Author: Shengchen Kan
Date: 2024-07-31T11:03:23+08:00
New Revision: 57acabb8e09baa38b156965b2dc567a8c7eb2429
URL:
https://github.com/llvm/llvm-project/commit/57acabb8e09baa38b156965b2dc567a8c7eb2429
DIFF:
https://github.com/llvm/llvm-project/commit/57acabb8e09baa38b156965b2dc567a8c7eb2429.diff
https://github.com/KanRobert closed
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Author: Shengchen Kan
Date: 2024-07-16T10:59:12+08:00
New Revision: d82c75ebc0483971b768dd5ff077789262ffd9c0
URL:
https://github.com/llvm/llvm-project/commit/d82c75ebc0483971b768dd5ff077789262ffd9c0
DIFF:
https://github.com/llvm/llvm-project/commit/d82c75ebc0483971b768dd5ff077789262ffd9c0.diff
@@ -175,8 +175,6 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",
34)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35)
// Below Features has some missings comparing to gcc, it's because gcc has some
// not one-to-one mapped in llvm.
-X86_FEATURE_
Author: Shengchen Kan
Date: 2024-07-19T12:34:41+08:00
New Revision: 88e9bd822fe088eff74f49081b890071538fa40c
URL:
https://github.com/llvm/llvm-project/commit/88e9bd822fe088eff74f49081b890071538fa40c
DIFF:
https://github.com/llvm/llvm-project/commit/88e9bd822fe088eff74f49081b890071538fa40c.diff
https://github.com/KanRobert approved this pull request.
LGTM. My understanding is that this flag is used for reducing compile time and
debug only.
https://github.com/llvm/llvm-project/pull/90013
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https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/106681
For
movname@GOTPCREL(%rip), %reg
test %reg, name@GOTPCREL(%rip)
binop name@GOTPCREL(%rip), %reg
where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructi
https://github.com/KanRobert converted_to_draft
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/2] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/3] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/4] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/106681
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KanRobert wrote:
TODO:
* [ ] Pass tests lld/test/ELF/x86-64-gotpc-relax.s and
lld/test/ELF/x86-64-gotpc-relax-nopic.s
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/5] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert ready_for_review
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/6] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/7] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
@@ -8359,6 +8359,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasFlag(options::OPT_msse2avx, options::OPT_mno_sse2avx, true))
+Args.addOptIn
@@ -5186,6 +5187,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag>;
+def msse2avx : Flag<["-"], "msse2avx">, Group,
@@ -5186,6 +5187,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag>;
+def msse2avx : Flag<["-"], "msse2avx">, Group,
@@ -8359,6 +8359,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasFlag(options::OPT_msse2avx, options::OPT_mno_sse2avx, true))
+Args.addOptIn
@@ -4761,6 +4761,7 @@ def mno_tls_direct_seg_refs : Flag<["-"],
"mno-tls-direct-seg-refs">, Group,
MarshallingInfoFlag>;
def mno_relax_all : Flag<["-"], "mno-relax-all">, Group;
+def mno_sse2avx : Flag<["-"], "mno-sse2avx">, Group;
KanRobert wrote:
I wonder
KanRobert wrote:
Don't add clang test in MC folder. You can add front-end tests to check the
flag is passed down correctly.
https://github.com/llvm/llvm-project/pull/96860
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KanRobert wrote:
> How easy would it be to add an option for this to update inline asm? I'm not
> asking you to do this here, I just want to know if this approach would make
> it straightforward to add in the future.
Should we touch the inline asm? (GCC doesn't https://godbolt.org/z/o9MM9br95
@@ -0,0 +1,89 @@
+# RUN: %clang -march=x86-64 -msse2avx %s -c -o %t
KanRobert wrote:
Do not add end2end test. Check test for other flags.
https://github.com/llvm/llvm-project/pull/96860
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KanRobert wrote:
Add -att suffix
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@@ -335,6 +337,31 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
+void X86InstrMappingEmitter::emitSSE2AVXTable(
+ArrayRef Insts, raw_ostream &OS) {
+ std::vector Table;
+ for (const CodeGenInst
@@ -5201,6 +5201,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag>;
+def msse2avx : Flag<["-"], "msse2avx">, Group,
+ Visibility<[C
KanRobert wrote:
Hmm, what's your usage?
#define A
before
#include
?
https://github.com/llvm/llvm-project/pull/98478
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@@ -335,6 +337,31 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
+void X86InstrMappingEmitter::emitSSE2AVXTable(
+ArrayRef Insts, raw_ostream &OS) {
+ std::vector Table;
+ for (const CodeGenInst
Martin =?utf-8?q?Storsj=C3=B6?=
Message-ID:
In-Reply-To:
https://github.com/KanRobert commented:
LGTM
https://github.com/llvm/llvm-project/pull/98478
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@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -8367,6 +8369,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasArg(options::OPT_msse2avx))
+Args.AddLastArg(CmdArgs, options::OPT_msse2avx
@@ -140,6 +141,10 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::init(true));
MCBINDOPT(X86RelaxRelocations);
+ static cl::opt X86Sse2Avx(
+ "x86-sse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
--
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
https://github.com/KanRobert deleted
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/96860
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https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/96860
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https://github.com/llvm/llvm-project/pull/96860
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https://github.com/llvm/llvm-project/pull/96860
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@@ -2711,6 +2711,8 @@ static void CollectArgsForIntegratedAssembler(Compilation
&C,
}
if (!UseRelaxRelocations)
CmdArgs.push_back("-mrelax-relocations=no");
+ if (Args.hasArg(options::OPT_msse2avx))
+CmdArgs.push_back("-msse2avx");
KanRobert wrote
@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl &Values) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
KanRobert
@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl &Values) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
KanRobert
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
I
@@ -83,8 +85,23 @@ const TargetInfo::AddlRegName AddlRegNames[] = {
{{"r13d", "r13w", "r13b"}, 43},
{{"r14d", "r14w", "r14b"}, 44},
{{"r15d", "r15w", "r15b"}, 45},
+{{"r16d", "r16w", "r16b"}, 165},
KanRobert wrote:
Where does the 165 come from?
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
We
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
Cr
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
ba
KanRobert wrote:
Rename it to inline-asm-gcc-regs.c?
https://github.com/llvm/llvm-project/pull/91323
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/91323
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Author: Shengchen Kan
Date: 2024-05-11T15:55:59+08:00
New Revision: 575177f610274e909a17450c29d2e997f7a7f13d
URL:
https://github.com/llvm/llvm-project/commit/575177f610274e909a17450c29d2e997f7a7f13d
DIFF:
https://github.com/llvm/llvm-project/commit/575177f610274e909a17450c29d2e997f7a7f13d.diff
KanRobert wrote:
Please put the corresponding GCC links for your description
https://github.com/llvm/llvm-project/pull/92338
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
This should not
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
```
std::stri
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
Will the featur
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> `mcmodel` may
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> > Will the fe
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> SSELevel reli
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