@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/66978
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ecnelises wrote:
The motivating case:
```llvm
define i64 @splatByte(i64 %a) {
entry:
%x0 = shl i64 %a, 8
%x1 = and i64 %a, 255
%x2 = or i64 %x0, %x1
%x3 = shl i64 %x2, 16
%x4 = and i64 %x2, 65535
%x5 = or i64 %x3, %x4
%x6 = shl i64 %x5, 32
%x7 = and i64 %x5, 4294967295
%x8 = or
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/76495
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/66040
>From ebaafdd6d45bb62b1847e60df627dfd96971a22c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 12 Sep 2023 10:39:55 +0800
Subject: [PATCH] [PowerPC] Check value uses in ValueBit tracking
---
llvm/lib/Ta
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/3] [PowerPC] Peephole address calculation in TOC memops
---
ll
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/4] [PowerPC] Peephole address calculation in TOC memops
---
ll
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/5] [PowerPC] Peephole address calculation in TOC memops
---
ll
@@ -442,19 +442,44 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
// _CALL_DARWIN
}
-// Handle explicit options being passed to the compiler here: if we've
-// explicitly turned off vsx and turned on any of:
-// - power8-vector
-// - direct-move
-// - fl
@@ -68,10 +68,10 @@ extern __inline __m128d
__asm__("mffsce %0" : "=f"(__fpscr_save.__fr));
__enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8;
#else
-__fpscr_save.__fr = __builtin_mffs();
+__fpscr_save.__fr = __builtin_ppc_mffs();
ecnelises w
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/67299
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https://github.com/llvm/llvm-project/pull/67829
>From 45906e0ec45c9302f4d9af10b94276c7f7185fef Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Sat, 30 Sep 2023 00:21:14 +0800
Subject: [PATCH 1/2] [DAGCombine] Fold setcc_eq infinity into is.fpclass
---
...
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/69432
>From f97807afc177ab04c97d0c346081fc92d3e79e6c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 18 Oct 2023 16:02:02 +0800
Subject: [PATCH 1/3] [Clang][Sema] Skip RecordDecl when checking scope of
declara
Author: Qiu Chaofan
Date: 2020-09-12T00:39:52+08:00
New Revision: 8ecc8520bc5bc20ae00c13e5ae13f8edbb80642e
URL:
https://github.com/llvm/llvm-project/commit/8ecc8520bc5bc20ae00c13e5ae13f8edbb80642e
DIFF:
https://github.com/llvm/llvm-project/commit/8ecc8520bc5bc20ae00c13e5ae13f8edbb80642e.diff
L
Author: Qiu Chaofan
Date: 2020-08-21T15:12:19+08:00
New Revision: 91039784b3c9757c35e348d4e0700c90adb1a7e7
URL:
https://github.com/llvm/llvm-project/commit/91039784b3c9757c35e348d4e0700c90adb1a7e7
DIFF:
https://github.com/llvm/llvm-project/commit/91039784b3c9757c35e348d4e0700c90adb1a7e7.diff
L
Author: Qiu Chaofan
Date: 2020-09-09T22:40:58+08:00
New Revision: 88ff4d2ca1a0aaed6888152042256a0ef3fe863d
URL:
https://github.com/llvm/llvm-project/commit/88ff4d2ca1a0aaed6888152042256a0ef3fe863d
DIFF:
https://github.com/llvm/llvm-project/commit/88ff4d2ca1a0aaed6888152042256a0ef3fe863d.diff
L
Author: Qiu Chaofan
Date: 2020-12-08T14:08:52+08:00
New Revision: 5e85a2ba1645c3edbf26bba096631fbd318ada47
URL:
https://github.com/llvm/llvm-project/commit/5e85a2ba1645c3edbf26bba096631fbd318ada47
DIFF:
https://github.com/llvm/llvm-project/commit/5e85a2ba1645c3edbf26bba096631fbd318ada47.diff
L
Author: Qiu Chaofan
Date: 2020-12-16T17:19:54+08:00
New Revision: f141d1afc5068d5c5e2c47e25a5d4b4914116b92
URL:
https://github.com/llvm/llvm-project/commit/f141d1afc5068d5c5e2c47e25a5d4b4914116b92
DIFF:
https://github.com/llvm/llvm-project/commit/f141d1afc5068d5c5e2c47e25a5d4b4914116b92.diff
L
Author: Qiu Chaofan
Date: 2020-11-04T17:58:42+08:00
New Revision: 7faf62a80bfc3a9dfe34133681fcc31f8e8d658b
URL:
https://github.com/llvm/llvm-project/commit/7faf62a80bfc3a9dfe34133681fcc31f8e8d658b
DIFF:
https://github.com/llvm/llvm-project/commit/7faf62a80bfc3a9dfe34133681fcc31f8e8d658b.diff
L
Author: Qiu Chaofan
Date: 2020-11-10T10:52:13+08:00
New Revision: 979a4d268a48c27d9c0dce642912bcf648614ef8
URL:
https://github.com/llvm/llvm-project/commit/979a4d268a48c27d9c0dce642912bcf648614ef8
DIFF:
https://github.com/llvm/llvm-project/commit/979a4d268a48c27d9c0dce642912bcf648614ef8.diff
L
Author: Qiu Chaofan
Date: 2020-11-12T10:26:13+08:00
New Revision: 2abc33683b2b702c00c366d56c6285fda6d1e436
URL:
https://github.com/llvm/llvm-project/commit/2abc33683b2b702c00c366d56c6285fda6d1e436
DIFF:
https://github.com/llvm/llvm-project/commit/2abc33683b2b702c00c366d56c6285fda6d1e436.diff
L
Author: Qiu Chaofan
Date: 2020-11-19T14:22:14+08:00
New Revision: 6b1341eb5bb71a1ce4547165a247b23bb30ef44e
URL:
https://github.com/llvm/llvm-project/commit/6b1341eb5bb71a1ce4547165a247b23bb30ef44e
DIFF:
https://github.com/llvm/llvm-project/commit/6b1341eb5bb71a1ce4547165a247b23bb30ef44e.diff
L
Author: Qiu Chaofan
Date: 2020-12-02T17:02:26+08:00
New Revision: 3fca6a7844b515496446667a18a9703c29cf6e88
URL:
https://github.com/llvm/llvm-project/commit/3fca6a7844b515496446667a18a9703c29cf6e88
DIFF:
https://github.com/llvm/llvm-project/commit/3fca6a7844b515496446667a18a9703c29cf6e88.diff
L
Author: Qiu Chaofan
Date: 2020-12-03T10:50:42+08:00
New Revision: 222da77a82d17cbc6b989779e2ba2bb4904bb672
URL:
https://github.com/llvm/llvm-project/commit/222da77a82d17cbc6b989779e2ba2bb4904bb672
DIFF:
https://github.com/llvm/llvm-project/commit/222da77a82d17cbc6b989779e2ba2bb4904bb672.diff
L
Author: Qiu Chaofan
Date: 2020-12-04T11:29:55+08:00
New Revision: 9378a366b2b256ebd1b2763141f683ab9b48c303
URL:
https://github.com/llvm/llvm-project/commit/9378a366b2b256ebd1b2763141f683ab9b48c303
DIFF:
https://github.com/llvm/llvm-project/commit/9378a366b2b256ebd1b2763141f683ab9b48c303.diff
L
Author: Qiu Chaofan
Date: 2020-12-07T18:31:00+08:00
New Revision: 6bf29dbb1541aff717e52b5c5fb12b84f5b38f21
URL:
https://github.com/llvm/llvm-project/commit/6bf29dbb1541aff717e52b5c5fb12b84f5b38f21
DIFF:
https://github.com/llvm/llvm-project/commit/6bf29dbb1541aff717e52b5c5fb12b84f5b38f21.diff
L
Author: Qiu Chaofan
Date: 2021-05-12T14:33:41+08:00
New Revision: febbe4b5a0ab0cb6f8ada6cd1ead4bb1f565bda8
URL:
https://github.com/llvm/llvm-project/commit/febbe4b5a0ab0cb6f8ada6cd1ead4bb1f565bda8
DIFF:
https://github.com/llvm/llvm-project/commit/febbe4b5a0ab0cb6f8ada6cd1ead4bb1f565bda8.diff
L
Author: Qiu Chaofan
Date: 2021-05-12T16:51:52+08:00
New Revision: cbd93cee9bf014402a7405479ba21f6f3340a126
URL:
https://github.com/llvm/llvm-project/commit/cbd93cee9bf014402a7405479ba21f6f3340a126
DIFF:
https://github.com/llvm/llvm-project/commit/cbd93cee9bf014402a7405479ba21f6f3340a126.diff
L
Author: Qiu Chaofan
Date: 2021-05-28T00:14:35+08:00
New Revision: 5c18d1136665f74b15c0df599f56ac3e2e947fb8
URL:
https://github.com/llvm/llvm-project/commit/5c18d1136665f74b15c0df599f56ac3e2e947fb8
DIFF:
https://github.com/llvm/llvm-project/commit/5c18d1136665f74b15c0df599f56ac3e2e947fb8.diff
L
Author: Qiu Chaofan
Date: 2021-06-01T01:19:12+08:00
New Revision: c0b3071833a80121a5a7ca9ea54fd59a59806acc
URL:
https://github.com/llvm/llvm-project/commit/c0b3071833a80121a5a7ca9ea54fd59a59806acc
DIFF:
https://github.com/llvm/llvm-project/commit/c0b3071833a80121a5a7ca9ea54fd59a59806acc.diff
L
Author: Qiu Chaofan
Date: 2021-02-05T20:33:56+08:00
New Revision: 447dc856b243b99ce70019ba1187c39746f4e0e9
URL:
https://github.com/llvm/llvm-project/commit/447dc856b243b99ce70019ba1187c39746f4e0e9
DIFF:
https://github.com/llvm/llvm-project/commit/447dc856b243b99ce70019ba1187c39746f4e0e9.diff
L
Author: Qiu Chaofan
Date: 2021-09-17T15:24:06+08:00
New Revision: 0195f8621f1814967f9cd3ef51ee61117e914299
URL:
https://github.com/llvm/llvm-project/commit/0195f8621f1814967f9cd3ef51ee61117e914299
DIFF:
https://github.com/llvm/llvm-project/commit/0195f8621f1814967f9cd3ef51ee61117e914299.diff
L
Author: Qiu Chaofan
Date: 2021-08-18T17:42:12+08:00
New Revision: 1d06a39d6ede7f641063e5dfccd145703ee20b98
URL:
https://github.com/llvm/llvm-project/commit/1d06a39d6ede7f641063e5dfccd145703ee20b98
DIFF:
https://github.com/llvm/llvm-project/commit/1d06a39d6ede7f641063e5dfccd145703ee20b98.diff
L
Author: Qiu Chaofan
Date: 2021-11-03T17:57:25+08:00
New Revision: 741aeda97d6327edd9905b21a5308fcee21bbefd
URL:
https://github.com/llvm/llvm-project/commit/741aeda97d6327edd9905b21a5308fcee21bbefd
DIFF:
https://github.com/llvm/llvm-project/commit/741aeda97d6327edd9905b21a5308fcee21bbefd.diff
L
Author: Qiu Chaofan
Date: 2021-12-03T17:50:18+08:00
New Revision: 4f94c02616025ace168899b6fbdc8c3ba240062b
URL:
https://github.com/llvm/llvm-project/commit/4f94c02616025ace168899b6fbdc8c3ba240062b
DIFF:
https://github.com/llvm/llvm-project/commit/4f94c02616025ace168899b6fbdc8c3ba240062b.diff
L
Author: Qiu Chaofan
Date: 2021-12-03T18:07:34+08:00
New Revision: b9adaa1782db727df08b8138e12c1e60964885d3
URL:
https://github.com/llvm/llvm-project/commit/b9adaa1782db727df08b8138e12c1e60964885d3
DIFF:
https://github.com/llvm/llvm-project/commit/b9adaa1782db727df08b8138e12c1e60964885d3.diff
L
Author: Qiu Chaofan
Date: 2022-12-19T15:22:39+08:00
New Revision: a40ef656d812143d24c810c65ebf6b24646837f0
URL:
https://github.com/llvm/llvm-project/commit/a40ef656d812143d24c810c65ebf6b24646837f0
DIFF:
https://github.com/llvm/llvm-project/commit/a40ef656d812143d24c810c65ebf6b24646837f0.diff
L
Author: Qiu Chaofan
Date: 2022-11-18T10:34:41+08:00
New Revision: cab9c02bd97f520cb8a01a9197505438581f7de8
URL:
https://github.com/llvm/llvm-project/commit/cab9c02bd97f520cb8a01a9197505438581f7de8
DIFF:
https://github.com/llvm/llvm-project/commit/cab9c02bd97f520cb8a01a9197505438581f7de8.diff
L
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/67298
PowerPC AIX backend does not support float128 at all. Diagnose even when
specifying -mfloat128 to avoid backend crash.
>From 58cd725354eae6aa733c98374a804de0ef595c60 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/67299
smmintrin.h uses __builtin_mffs, __builtin_mffsl, __builtin_mtfsf and
__builtin_set_fpscr_rn. This patch replaces the uses with ppc prefix and
implement the missing ones.
This fixes issue #64664.
>From 5abcf
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/67299
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Author: Qiu Chaofan
Date: 2023-09-25T17:53:39+08:00
New Revision: 3e97db89ae8e5b4d7bb6c0bf52773c43c9e06c51
URL:
https://github.com/llvm/llvm-project/commit/3e97db89ae8e5b4d7bb6c0bf52773c43c9e06c51
DIFF:
https://github.com/llvm/llvm-project/commit/3e97db89ae8e5b4d7bb6c0bf52773c43c9e06c51.diff
L
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/67299
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Author: Qiu Chaofan
Date: 2023-08-16T18:15:08+08:00
New Revision: 2459ed67805c1c6bd9d7db2f1e481b318960d7d8
URL:
https://github.com/llvm/llvm-project/commit/2459ed67805c1c6bd9d7db2f1e481b318960d7d8
DIFF:
https://github.com/llvm/llvm-project/commit/2459ed67805c1c6bd9d7db2f1e481b318960d7d8.diff
L
@@ -68,10 +68,10 @@ extern __inline __m128d
__asm__("mffsce %0" : "=f"(__fpscr_save.__fr));
__enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8;
#else
-__fpscr_save.__fr = __builtin_mffs();
+__fpscr_save.__fr = __builtin_ppc_mffs();
ecnelises w
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67299
>From 2d628587b9cede36e7a93ecb1414cc0c16596934 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:06:26 +0800
Subject: [PATCH 1/2] [PowerPC] Fix use of FPSCR builtins in smmintrin.h
smmintrin
@@ -219,9 +234,14 @@ extern __inline __m128
*/
__asm__("" : : "wa"(__r));
/* Restore enabled exceptions. */
-__fpscr_save.__fr = __builtin_mffsl();
+#ifdef _ARCH_PWR9
+__fpscr_save.__fr = __builtin_ppc_mffsl();
+#else
+__fpscr_save.__fr = __builtin_ppc
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/2] [Legalizer] Expand fmaximum and fminimum
According to langre
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/2] [Legalizer] Expand fmaximum and fminimum
According to langre
@@ -8177,6 +8177,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
ecnelises wrote:
Can MIR be valid input for legalizers? I see MIR outputs are all legalized.
@@ -8177,6 +8177,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
ecnelises wrote:
Can MIR be valid input for legalizers? I see MIR outputs are all legalized.
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/68678
Currently targets except AArch64 cannot recognize function attribute specifying
target CPU. Make it equivalent to `arch` directive.
>From 78f22a8a57f5b67660763b8c7731b9d3cddede72 Mon Sep 17 00:00:00 2001
From:
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/68681
None
>From c1fbd4242c135ecbf91882d0350dc7d4c1e84b69 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 10 Oct 2023 17:50:59 +0800
Subject: [PATCH] [Clang][PowerPC] Support tune directive in target attribute
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/68681
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/68678
>From 78f22a8a57f5b67660763b8c7731b9d3cddede72 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 10 Oct 2023 17:20:00 +0800
Subject: [PATCH 1/2] [Clang] Support target attr specifying CPU
Currently targets
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/68861
Tune CPU relies on model of instruction sets. Compiler should warn if not all
instruction sets of current target CPU are supported by tune CPU. Although
there is limitation that Clang cannot analyze actual req
ecnelises wrote:
Does backend have any recognition of Haiku-PPC target?
https://github.com/llvm/llvm-project/pull/69134
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/68678
>From 78f22a8a57f5b67660763b8c7731b9d3cddede72 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 10 Oct 2023 17:20:00 +0800
Subject: [PATCH 1/3] [Clang] Support target attr specifying CPU
Currently targets
@@ -76,10 +80,14 @@ int __attribute__((target("fpmath=387"))) walrus(void) {
return 4; }
int __attribute__((target("float128,arch=hiss"))) meow(void) { return 4; }
// no warning, same as saying 'nothing'.
int __attribute__((target("arch="))) turtle(void) { return 4; }
+// no
@@ -11595,6 +11595,50 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op,
SelectionDAG &DAG) const {
llvm_unreachable("ERROR:Should return for all cases within swtich.");
}
+// Lower mffsl intrinsic with mffs in targets without ISA 3.0
+static SDValue lowerMFFSL(SDValu
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67299
>From 2d628587b9cede36e7a93ecb1414cc0c16596934 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:06:26 +0800
Subject: [PATCH 1/3] [PowerPC] Fix use of FPSCR builtins in smmintrin.h
smmintrin
@@ -2420,11 +2420,11 @@ command line.
The current set of options correspond to the existing "subtarget features" for
the target with or without a "-mno-" in front corresponding to the absence
-of the feature, as well as ``arch="CPU"`` which will change the default "CPU"
-for t
@@ -2420,11 +2420,11 @@ command line.
The current set of options correspond to the existing "subtarget features" for
the target with or without a "-mno-" in front corresponding to the absence
-of the feature, as well as ``arch="CPU"`` which will change the default "CPU"
-for t
@@ -833,6 +833,22 @@ TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
if (!Target->handleTargetFeatures(Opts->Features, Diags))
return nullptr;
+ // If TuneCPU is set, check if it contains all instruction sets needed by
+ // current feature map.
+ if (!Opts->Tun
ecnelises wrote:
Ah, I meant potential changes to `llvm/lib/Target` and `llvm/lib/MC`. But I did
search in backend using FreeBSD as keyword for example, few places need to
support it explicitly. If Haiku uses similar ABI and binary format to Linux or
FreeBSD, that makes sense.
https://github.
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/69432
In non C++ mode, struct definitions does not create a scope for declaration.
Fixes #41302
Fixes #44080
>From 6828025e788347f21a41d4a9aa138af032017b80 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 18
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/69432
>From f97807afc177ab04c97d0c346081fc92d3e79e6c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 18 Oct 2023 16:02:02 +0800
Subject: [PATCH] [Clang][Sema] Skip RecordDecl when checking scope of
declaration
Author: Qiu Chaofan
Date: 2023-09-05T10:57:37+08:00
New Revision: 880f39af6115184ccd1950ff263b7c43993cd438
URL:
https://github.com/llvm/llvm-project/commit/880f39af6115184ccd1950ff263b7c43993cd438
DIFF:
https://github.com/llvm/llvm-project/commit/880f39af6115184ccd1950ff263b7c43993cd438.diff
L
Author: Qiu Chaofan
Date: 2023-09-05T11:22:09+08:00
New Revision: 082c5d7f63c490af69e8280e5b5ff6bf6051bd59
URL:
https://github.com/llvm/llvm-project/commit/082c5d7f63c490af69e8280e5b5ff6bf6051bd59
DIFF:
https://github.com/llvm/llvm-project/commit/082c5d7f63c490af69e8280e5b5ff6bf6051bd59.diff
L
Author: Qiu Chaofan
Date: 2020-01-27T11:37:43+08:00
New Revision: 59d690850eebcd0e37f205bde16edbd4f2a54053
URL:
https://github.com/llvm/llvm-project/commit/59d690850eebcd0e37f205bde16edbd4f2a54053
DIFF:
https://github.com/llvm/llvm-project/commit/59d690850eebcd0e37f205bde16edbd4f2a54053.diff
L
Author: Qiu Chaofan
Date: 2023-03-15T14:21:52+08:00
New Revision: 608212a0ff2f9e9a2cee8b5b0fa206fd15eb6472
URL:
https://github.com/llvm/llvm-project/commit/608212a0ff2f9e9a2cee8b5b0fa206fd15eb6472
DIFF:
https://github.com/llvm/llvm-project/commit/608212a0ff2f9e9a2cee8b5b0fa206fd15eb6472.diff
L
Author: Qiu Chaofan
Date: 2023-05-23T16:35:25+08:00
New Revision: baeb85b5a99778956117d647b78b55be4f51a129
URL:
https://github.com/llvm/llvm-project/commit/baeb85b5a99778956117d647b78b55be4f51a129
DIFF:
https://github.com/llvm/llvm-project/commit/baeb85b5a99778956117d647b78b55be4f51a129.diff
L
Author: Tulio Magno Quites Machado Filho
Date: 2023-02-14T15:03:58+08:00
New Revision: cb90bb986611bab58dbe05cefb0903e0a07f3cca
URL:
https://github.com/llvm/llvm-project/commit/cb90bb986611bab58dbe05cefb0903e0a07f3cca
DIFF:
https://github.com/llvm/llvm-project/commit/cb90bb986611bab58dbe05cefb0
Author: Qiu Chaofan
Date: 2022-12-07T16:44:12+08:00
New Revision: 62f20f51ce39560e439f522536e0bf1e2f1f9fa9
URL:
https://github.com/llvm/llvm-project/commit/62f20f51ce39560e439f522536e0bf1e2f1f9fa9
DIFF:
https://github.com/llvm/llvm-project/commit/62f20f51ce39560e439f522536e0bf1e2f1f9fa9.diff
L
Author: Tulio Magno Quites Machado Filho
Date: 2022-12-14T11:13:54+08:00
New Revision: 5f68c4111ab9c79b902723df3986dd1033813c01
URL:
https://github.com/llvm/llvm-project/commit/5f68c4111ab9c79b902723df3986dd1033813c01
DIFF:
https://github.com/llvm/llvm-project/commit/5f68c4111ab9c79b902723df398
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/97524
In PowerPC ABI, a few initial arguments are passed through registers, but their
places in parameter save area are reserved, arguments passed by memory goes
after the reserved location.
For debugging purpose,
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/97524
>From 654cf7753023302c367340872e889856f8738169 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 3 Jul 2024 14:17:01 +0800
Subject: [PATCH] [AIX] Add -msave-reg-params to save arguments to stack
In PowerPC
@@ -0,0 +1,37 @@
+//=== PPCTargetParser - Parser for target features --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/ecnelises converted_to_draft
https://github.com/llvm/llvm-project/pull/97524
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/97524
>From 654cf7753023302c367340872e889856f8738169 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 3 Jul 2024 14:17:01 +0800
Subject: [PATCH 1/2] [AIX] Add -msave-reg-params to save arguments to stack
In Pow
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/73750
>From db3bd53b27ee5fcb0572e0a43ca4cd4ed1376e65 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 10 Sep 2024 15:25:37 +0800
Subject: [PATCH] [PowerPC] Support set_flt_rounds builtin
---
clang/docs/Languag
https://github.com/ecnelises ready_for_review
https://github.com/llvm/llvm-project/pull/73750
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ecnelises wrote:
@llvm/pr-subscribers-backend-powerpc
https://github.com/llvm/llvm-project/pull/68861
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https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/86783
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https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/94581
None
>From 4e078099d8e15fd984ef38435d6f792bbb3d754c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 6 Jun 2024 14:06:48 +0800
Subject: [PATCH] [PowerPC] Support -mno-red-zone option
---
clang/lib/Drive
ecnelises wrote:
No. `-disable-red-zone` does nothing but add `noredzone` IR attribute to
functions. We need to add cases to test for `noredzone` behavior on PPC (arm
and x86 have).
https://github.com/llvm/llvm-project/pull/94581
___
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/94581
>From 4e078099d8e15fd984ef38435d6f792bbb3d754c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 6 Jun 2024 14:06:48 +0800
Subject: [PATCH 1/2] [PowerPC] Support -mno-red-zone option
---
clang/lib/Driver/
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/97524
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https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/97524
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https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
ecnelises wrote:
Thanks for pointing LTO stuff out. Do you mean the module flags might be
messed up when merging in LTO? I thought a file level codegen option can be
mapped to a module level flag.
https://github.com/llvm/llvm-project/pull/97524
___
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/97524
>From 654cf7753023302c367340872e889856f8738169 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 3 Jul 2024 14:17:01 +0800
Subject: [PATCH 1/3] [AIX] Add -msave-reg-params to save arguments to stack
In Pow
https://github.com/ecnelises ready_for_review
https://github.com/llvm/llvm-project/pull/97524
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@@ -515,6 +515,16 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "",
"power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
+// P7 BCD builtins.
+TARGET_BUI
Author: Qiu Chaofan
Date: 2022-01-24T15:23:28+08:00
New Revision: c5590396d041e77a84101cdcc4249788403e4e40
URL:
https://github.com/llvm/llvm-project/commit/c5590396d041e77a84101cdcc4249788403e4e40
DIFF:
https://github.com/llvm/llvm-project/commit/c5590396d041e77a84101cdcc4249788403e4e40.diff
L
Author: Qiu Chaofan
Date: 2022-01-26T15:19:22+08:00
New Revision: f563bd74cb9a4f0d2d3eb49d35536b648361ec53
URL:
https://github.com/llvm/llvm-project/commit/f563bd74cb9a4f0d2d3eb49d35536b648361ec53
DIFF:
https://github.com/llvm/llvm-project/commit/f563bd74cb9a4f0d2d3eb49d35536b648361ec53.diff
L
Author: Qiu Chaofan
Date: 2022-01-27T00:50:53+08:00
New Revision: b797d5e6b21b3af3d581642c9a535327aa0764a7
URL:
https://github.com/llvm/llvm-project/commit/b797d5e6b21b3af3d581642c9a535327aa0764a7
DIFF:
https://github.com/llvm/llvm-project/commit/b797d5e6b21b3af3d581642c9a535327aa0764a7.diff
L
Author: Qiu Chaofan
Date: 2022-03-07T13:00:06+08:00
New Revision: b2497e54356d454d0e16d8f44086bf6db6aff0e3
URL:
https://github.com/llvm/llvm-project/commit/b2497e54356d454d0e16d8f44086bf6db6aff0e3
DIFF:
https://github.com/llvm/llvm-project/commit/b2497e54356d454d0e16d8f44086bf6db6aff0e3.diff
L
Author: Qiu Chaofan
Date: 2022-01-07T15:52:59+08:00
New Revision: c2cc70e4f534f445693d4ffb6fb8955c3e0bc2be
URL:
https://github.com/llvm/llvm-project/commit/c2cc70e4f534f445693d4ffb6fb8955c3e0bc2be
DIFF:
https://github.com/llvm/llvm-project/commit/c2cc70e4f534f445693d4ffb6fb8955c3e0bc2be.diff
L
Author: Qiu Chaofan
Date: 2022-01-17T15:12:33+08:00
New Revision: d771cf277565f579aba24fef522355f4406323c9
URL:
https://github.com/llvm/llvm-project/commit/d771cf277565f579aba24fef522355f4406323c9
DIFF:
https://github.com/llvm/llvm-project/commit/d771cf277565f579aba24fef522355f4406323c9.diff
L
Author: Qiu Chaofan
Date: 2021-12-10T16:02:53+08:00
New Revision: d3cd0635e15a16fdf890c79035438c0f7c0d63b1
URL:
https://github.com/llvm/llvm-project/commit/d3cd0635e15a16fdf890c79035438c0f7c0d63b1
DIFF:
https://github.com/llvm/llvm-project/commit/d3cd0635e15a16fdf890c79035438c0f7c0d63b1.diff
L
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