[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in { def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; } // TargetPrefix = "riscv" +// Zihintpause extensions +//===--===// +let TargetPrefix = "riscv" in { -

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -2198,6 +2198,15 @@ def : Pat<(binop_allwusers GPR:$rs1, immop_oneuse:$rs2), def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>; } +//===--===// +// Zihintpause +//===---

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,153 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [RISC-V] Allow intrinsics to be used with any pointer type. (PR #139634)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139634 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ wangpc-pp wrote: riscv64 RUN as well. https://github.com/llvm/llvm-project/pull

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp commented: Do we need a header for it (just like others in https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#intrinsic-functions)? https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits ma

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include wangpc-pp wrote: Remove this include.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,17 @@ +//===-- RISCVInstrInfoZihintpause.td ---*- tablegen -*-===// wangpc-pp wrote: This file is too small, we may not need a standalone file for `Zihintpause`. You can put this pattern to llvm/lib/Target/RISCV/RISCVInstrInfo.td

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -291,6 +291,13 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; +def FeatureStdExtQ +: RISCVExtension<2, 2, "Quad-Precisio

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/133031 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

@@ -0,0 +1,11 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only -verify + +#include + +// expected-no-diagnostics + +__attribute__((target("arch=+zvl128b"))) +void test_zvk_features(vuint32m1_t vd, vuint32m1_t v

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/141548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AArch64] Add option -msve-streaming-vector-bits= . (PR #144611)

@@ -1034,9 +1034,16 @@ class TargetInfo : public TransferrableTargetInfo, /// set of primary and secondary targets. virtual llvm::SmallVector getTargetBuiltins() const = 0; + enum class ArmStreamingKind { +NotStreaming, +StreamingCompatible, +Streaming, + };

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/144063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AArch64] Add option -msve-streaming-vector-bits= . (PR #144611)

@@ -1034,9 +1034,16 @@ class TargetInfo : public TransferrableTargetInfo, /// set of primary and secondary targets. virtual llvm::SmallVector getTargetBuiltins() const = 0; + enum class ArmStreamingKind { +NotStreaming, +StreamingCompatible, +Streaming, + };

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -143,52 +143,82 @@ void __attribute__((riscv_vls_cc)) test_too_large(int32x64_t arg) {} // CHECK-LLVM: define dso_local riscv_vls_cc(256) void @test_too_large_256( noundef %arg.coerce) void __attribute__((riscv_vls_cc(256))) test_too_large_256(int32x64_t arg) {} -// CHECK

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/145267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

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[clang] [RISCV] Decrease the capacity of SmallVector to 6. NFC. (PR #145650)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/145650 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm][RISCV] Handle required features of intrinsic correctly (PR #143062)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/143062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

@@ -0,0 +1,33 @@ +// RUN: %clang --target=riscv64 -mcpu=andes-ax45mpv --print-enabled-extensions | FileCheck %s wangpc-pp wrote: Is that necessary to add a new file for each CPU? https://github.com/llvm/llvm-project/pull/145267 _

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

wangpc-pp wrote: Not related to this PR, but I'd like to raise the question here: For configurable cores, what is the best way to specify the features? `-mcpu` is meant to support the base configuration, but how can we specify the additional optional extensions? Apparently, failing back to `-m

[clang] [llvm] [RISCV] Add SiFive X390 processor definition (PR #142517)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/142517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add shlcofideleg extension (PR #141572)

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[clang] [RISCV] Use StringRef for RequiredExtensions in RVVIntrinsicDef (PR #143503)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/143503 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

@@ -0,0 +1,29 @@ +//==- BuiltinsRISCVXAndes.td - RISC-V Andes Builtin database -*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

@@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xandesperf -emit-llvm %s -o - \ wangpc-pp wrote: Run mem2ssa? https://github.com/llvm/llvm-project/pull/147018

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

wangpc-pp wrote: Should we document this in https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc? https://github.com/llvm/llvm-project/pull/147018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-

[clang] [llvm] [RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (PR #148563)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/148563 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add -march=unset to cancel and ignore a previous -march. (PR #148321)

https://github.com/wangpc-pp approved this pull request. LGTM and I totally support this! https://github.com/llvm/llvm-project/pull/148321 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commi

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

wangpc-pp wrote: > > > > This adds the support of Zibi v0.1 experimental extension. > > > > References: > > > > > > > > * > > > > https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan > > > > > > > > > I cannot for the life of me find an

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/147005 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -0,0 +1,44 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

https://github.com/wangpc-pp commented: How are we going to verify the correctness? Does qemu support big-endian riscv64? https://github.com/llvm/llvm-project/pull/146534 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

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