@@ -0,0 +1,27 @@
+//===-- lib/extendhfdf2.c - half -> single conversion -*- C
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
JonPsson1 wrote:
-- A few more tests added covering
alloca
access into aggregate type with half elements with getelementptr.
atomicrmw
Would a test for { half, half, half, half } in Swift-return.ll make sense?
I think testing coverage now is fairly ok - can't think of any more
instructions to
JonPsson1 wrote:
> Does s390x have +soft-float or any features that toggle the availability of
> float conversion ops?
Yes, we support soft-float, and as I wrote earlier I am worried what happens
with soft-float and conversion functions. I saw that with soft-float, the same
conversion functi
JonPsson1 wrote:
> What is needed to move this forward?
The review is in progress so this should hopefully land quite soon.
https://github.com/llvm/llvm-project/pull/109164
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@@ -229,7 +229,7 @@ class TargetInfo : public TransferrableTargetInfo,
bool NoAsmVariants; // True if {|} are normal characters.
bool HasLegalHalfType; // True if the backend supports operations on the half
// LLVM IR type.
- bool HalfArgsAndRetur
@@ -35,100 +35,96 @@ using namespace llvm;
#include "SystemZGenRegisterInfo.inc"
const unsigned SystemZMC::GR32Regs[16] = {
- SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
- SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
- SystemZ::R8L, SystemZ::R9L, Syst
@@ -65,6 +65,7 @@ void __clear_cache(void *start, void *end) {
#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
FlushInstructionCache(GetCurrentProcess(), start, end - start);
#elif defined(__arm__) && !defined(__APPLE__)
+#elif defined(__s390__)
--
@@ -179,20 +179,31 @@ bool SystemZABIInfo::isVectorArgumentType(QualType Ty)
const {
getContext().getTypeSize(Ty) <= 128);
}
-bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
+// The Size argument will in case of af an overaligned single element struct
+//
@@ -6470,6 +6540,84 @@ static SDValue lowerAddrSpaceCast(SDValue Op,
SelectionDAG &DAG) {
return Op;
}
+SDValue SystemZTargetLowering::lowerFP_EXTEND(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDValue In = Op.getOperand(Op->isSt
@@ -3830,6 +3876,14 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
ISD::CondCode CC = cast(Op.getOperand(4))->get();
SDLoc DL(Op);
+ // SELECT_CC involving f16 will not have the cmp-ops promoted by the
+ // legalizer, as it will be handled according to the
@@ -255,4 +255,9 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
}
setLibcallName(RTLIB::MULO_I128, nullptr);
}
+
+ if (TT.isSystemZ()) {
+setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
+setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfs
@@ -255,4 +255,9 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
}
setLibcallName(RTLIB::MULO_I128, nullptr);
}
+
+ if (TT.isSystemZ()) {
+setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
+setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfs
JonPsson1 wrote:
Patch rebased as the handling of libcalls had changed on main.
https://github.com/llvm/llvm-project/pull/109164
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JonPsson1 wrote:
Found one intrinsic that isn't working for f16:
- Isel fails:
%res = call i32 @llvm.s390.tdc.f16(half %x, i64 123)
LLVM ERROR: Cannot select: t9: i32 = SystemZISD::TDC t2, Constant:i64<123>
- The SystemZTDC pass seems to work with 'half', but no tests.
- The Clang testFPKind d
JonPsson1 wrote:
Patch rebased.
The reported formatting issue here is in the test which however was mostly
copied from a pre-existing test, so maybe clang-format should be done on all
these tests or not. Skipping it for now.
https://github.com/llvm/llvm-project/pull/109164
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@@ -126,3 +138,23 @@ define void @f9(ptr %cptr, ptr %aptr, ptr %bptr) {
store fp128 %c, ptr %cptr
ret void
}
+
+; Test f16 copies in which the sign comes from an f16.
+define half @f10(half %a, half %b) {
+; CHECK-LABEL: f10:
+; CHECK: brasl %r14, copysignh@PLT
JonPsson1 wrote:
Updated per review.
- Custom handlings added to deal with non-existing library functions:
FP_TO_INT:
Z10 unsigned:
Expanding fp-> i32/i64 seems to work best to do without first doing the custom
extension to f32 in the f16 input case. TargetLowering::expandFP_TO_UINT() can
@@ -0,0 +1,63 @@
+# RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs \
+# RUN: -start-before=greedy | FileCheck %s -check-prefix=CHECK
+# RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z16 -verify-machineinstrs \
+# RUN: -start-before=greedy | FileC
@@ -87,6 +90,15 @@ define <2 x double> @f7(<2 x double> %dummy, <2 x double>
%val1,
ret <2 x double> %ret
}
+; Test the fminh library function.
+define half @f11_half(half %dummy, half %val1, half %val2) {
+; CHECK-LABEL: f11_half:
+; CHECK: %r14, fminh@PLT
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=NOVEC
+; RUN: llc < %s -mtriple=s390x-linux-
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