[PATCH] D99984: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:259 .Case("riscv64", Is64Bit) + .Case("64bit", Is64Bit) .Case("m", HasM) frasercrmck wrote: > craig.topper wrote: > > frasercrmck wrote: > > > What's the differen

[PATCH] D100120: [RISCV][Clang] Add all RVV Mask intrinsic functions.

craig.topper added a comment. LGTM other than that inheritance question Comment at: clang/include/clang/Basic/riscv_vector.td:247 +list> suffixes_prototypes> { + defm "" : RVVBuiltinSet; +} Can we use inheritance here? Repository:

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:767 + // Rocketlake + list RKLAdditionalFeatures = [FeatureAES, + FeatureXSAVEC, FreddyYe wrote: > craig.topper wrote: > > Is this list t

[PATCH] D99984: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

This revision was automatically updated to reflect the committed changes. Closed by commit rG02ef9963e1ad: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D100127: [RISCV][Clang] Add some RVV Permutation intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100127/new/ https://reviews.llvm.org/D100127 ___

[PATCH] D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.

craig.topper added a comment. I think I wouldn't mind if we just didn't emit aligned loads/store instructions for AVX/AVX512 from isel and other places in the compiler in the first place. As noted, if the load gets folded the alignment check doesn't happen. That would reduce the size of the ise

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:271 "Invalidate Process-Context Identifier">; -def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", - "Enable Software

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:271-273 -def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", - "Enable Software Guard Extensions">; def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "

[PATCH] D100120: [RISCV][Clang] Add all RVV Mask intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100120/new/ https://reviews.llvm.org/D100120 ___

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:742 FeatureGFNI, FeatureCLWB, FeatureRDPID,

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:742 FeatureGFNI, FeatureCLWB, FeatureRDPID,

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:742 FeatureGFNI, FeatureCLWB, FeatureRDPID,

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added a comment. Thanks. I also found this https://github.com/gcc-mirror/gcc/commit/c422e5f81f42a0fc197f0715f4fcd81f1be90bff can you create a new patch to do the same for llvm/clang and rebase this patch on top of it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST AC

[PATCH] D100279: [X86] Remove FeatureCLWB from FeaturesICLClient

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100279/new/ https://reviews.llvm.org/D100279 ___

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100085/new/ https://reviews.llvm.org/D100085 ___

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100266/new/ https://reviews.llvm.org/D100266 ___

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: llvm/lib/Support/X86TargetParser.cpp:176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | FeatureXSAVES | FeatureSGX; // SkylakeServer inherits all SkylakeClient features except SGX. s

[PATCH] D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.

craig.topper added inline comments. Comment at: clang/include/clang/Driver/Options.td:1649 +Group, Flags<[CoreOption, HelpHidden]>, +HelpText<"Do not emit unaligned move instructions unless users explicitly uses.">; def fassociative_math : Flag<["-"], "fassociative-mat

[PATCH] D100368: [X86] Support some missing intrinsics

craig.topper added a comment. In D100368#2685559 , @LiuChen3 wrote: > In D100368#2685189 , @RKSimon wrote: > >> Add _mm512_i32loscatter_epi64 and _mm512_mask_i32loscatter_epi64 for >> completeness? > > It seems

[PATCH] D97764: [clang][patch] To solve PR26413, x86 interrupt routines may only call routines with no_saved_reg

craig.topper added a comment. In D97764#2685655 , @mibintc wrote: > I received a bug report that this patch creates error diagnostics for calls > to a builtin, like calling 'abort', 'exit' or one of the target builtins like > __builtin_ia32_packssw then

[PATCH] D97764: [clang][patch] To solve PR26413, x86 interrupt routines may only call routines with no_saved_reg

craig.topper added a comment. In D97764#2685841 , @mibintc wrote: > In D97764#2685742 , @craig.topper > wrote: > >> In D97764#2685655 , @mibintc wrote: >> >>> I received a b

[PATCH] D100391: [RISCV][Clang] Add RVV miscellaneous intrinsic functions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:97 +// type (SEW and LMUL), and computes another vector type which only changed +// SEW as given value. Ingore to define a new builtin if its qeuivalent +// type has illegal

[PATCH] D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:1723 + if (Args.hasArg(options::OPT_fuse_unaligned_vector_move)) +addArg(Twine("-x86-enable-unaligned-vector-move=true")); + else if (Args.hasArg(options::OPT_fno_use_unaligned_vector

[PATCH] D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.

craig.topper added inline comments. Comment at: clang/include/clang/Driver/Options.td:1649 +Group, Flags<[CoreOption, HelpHidden]>, +HelpText<"Do not emit unaligned move instructions unless users explicitly uses.">; def fassociative_math : Flag<["-"], "fassociative-mat

[PATCH] D100368: [X86] Support some missing intrinsics

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fintrin.h:9593 +/// locations starting at location \a base_addr at packed 32-bit integer indices +/// stored in the lower half of \a vindex scaled by \a scale them in dst. +/// "scale them i

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

craig.topper added a comment. In D99741#2690124 , @thakis wrote: > One of the ten commits that landed here > (https://github.com/llvm/llvm-project/compare/a3bfddbb6a27...59d5b8c27b43), > this being one of them, slowed down check-clang by over 20%: > htt

[PATCH] D100616: [clang] Fix a potential assert failure

craig.topper added a comment. In D100616#2693595 , @MaskRay wrote: > SVE::FirstTSBuiltin is 8148, the largest. Isn't SVE::FirstTSBuiltin used to start AArch64's builtins list. So shouldn't AArch64::LastTSBuiltin be larger? Repository: rG LLVM Github

[PATCH] D100616: [clang] Fix a potential assert failure

craig.topper added a comment. In D100616#2693607 , @MaskRay wrote: > In D100616#2693603 , @craig.topper > wrote: > >> In D100616#2693595 , @MaskRay >> wrote: >> >>> SVE:

[PATCH] D100391: [RISCV][Clang] Add RVV miscellaneous intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100391/new/ https://reviews.llvm.org/D100391 ___

[PATCH] D100617: [RISCV][Clang] Drop the assembly tests for RVV intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100617/new/ https://reviews.llvm.org/D100617 ___

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll:25 + %1 = bitcast i32 %b.coerce to <4 x i8> + %2 = tail call <4 x i8> @llvm.riscv.add8.v4i8(<4 x i8> %0, <4 x i8> %1) + %3 = bitcast <4 x i8> %2 to i32 I'm still no

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added a comment. Also can you please explain the vector codegen plan at a high level? Do you intend to support auto vectorization or just using vector_size in C? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/Builtins.def:41 // E -> ext_vector, followed by the number of elements and the base type. +// e -> Register sized Vector, followd by the base type and +// its width is the same as the register size

[PATCH] D100616: [clang][NFC] Fix a potential assert failure

craig.topper accepted this revision. craig.topper added a comment. LGTM. Thanks for removing the NEON and SVE. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100616/new/ https://reviews.llvm.org/D100616 ___ cfe-commits mailing list cfe-commits

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

craig.topper added a comment. In D99741#2701398 , @thakis wrote: >>> I think maybe reverting is not a good idea if we have a good progress on >>> this slow down issue. >> >> Yes, if we can fix the regression in a few days, then all is good. > > Another pi

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:33 def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>; +def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>; +def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTInt

[PATCH] D100822: [RISCV] Implement the vfabs.v/vfneg.v builtin.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100822/new/ https://reviews.llvm.org/D100822 ___

[PATCH] D100820: [RISCV] Implement the vnot.v builtin.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100820/new/ https://reviews.llvm.org/D100820 ___

[PATCH] D100823: [RISCV] Implement the pseudo compare builtin.

craig.topper added a comment. Thinking about this more, I'd like to consider doing this in the backend specifically for the compares for a few reasons. -vmsgt(u).vv intrinsic already selects vmslt(u).vv with swapped operands in the backend. This was needed for SEW=64 on RV32. -Inconsistent that

[PATCH] D100823: [RISCV] Implement the pseudo compare builtin.

craig.topper added a comment. I just posted https://reviews.llvm.org/D100889 which should allow the frontend to treat all comparisons the same way. It also avoids using the long expansion for vmsge.vx Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D100819: [RISCV] Implement the vneg.v builtin.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1048 + return Cmp < 0; + // Some mask intrinsics use the same IRName as unmasked. + // Sort the unmasked intrinsics first.

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100830/new/ https://reviews.llvm.org/D100830 ___

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

craig.topper added a comment. @rsmith or @rjmccall do you have any opinions on whether we should use builtin types like SVE or create a new attribute for RISCV? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new/ https://reviews.llvm.org/D92715 ___

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:943 +static MCRegister convertGPRToGPRPD(MCRegister Reg) { + assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && !((Reg - RISCV::X0) & 1) && + "Invalid register");

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

craig.topper added a comment. Ping CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new/ https://reviews.llvm.org/D92715 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92812/new/ https://reviews.llvm.org/D92812 _

[PATCH] D86855: Convert __m64 intrinsics to unconditionally use SSE2 instead of MMX instructions.

craig.topper added inline comments. Comment at: clang/lib/Headers/mmintrin.h:1264 { -return (__m64)__builtin_ia32_pcmpgtw((__v4hi)__m1, (__v4hi)__m2); +return (__m64)((__v4hi)__m1 > (__v4hi)__m2); } jyknight wrote: > craig.topper wrote: > > Same here >

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

craig.topper created this revision. craig.topper added reviewers: asb, lenary, frasercrmck, luismarques, kito-cheng. Herald added subscribers: NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

craig.topper created this revision. craig.topper added reviewers: asb, luismarques, frasercrmck, lewis-revill, simoncook, PaoloS, kito-cheng. Herald added subscribers: NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added a comment. This is a very incomplete review, but I need to go eat dinner Comment at: clang/include/clang/Basic/riscv_vector.td:201 +// gen-riscv-vector-test. +// gen-riscv-v-tests.sh will define each marco to generate each intrinsic test +// in different file

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:70 + // passing to the BUILTIN() macro in Builtins.def. + std::string builtin_str() const { return BuiltinStr; } + Return a const std::string & or a StringRef.

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:687 + [this](const std::vector &IntrinsicTypes) { +std::string S = " ID = Intrinsic::riscv_" + getIRName() + ";\n"; + Might be better to use raw_string_ostream he

[PATCH] D94582: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.

craig.topper updated this revision to Diff 318032. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94582/new/ https://reviews.llvm.org/D94582

[PATCH] D94582: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.

craig.topper updated this revision to Diff 318037. craig.topper added a comment. Remove Zba changes that accidentally got merged in the previous rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94582/new/ https://reviews.llvm.org/D94582 Files:

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

craig.topper updated this revision to Diff 318038. craig.topper added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94617/new/ https://reviews.llvm.org/D94617 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Drive

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:881 +if (!Def->hasSideEffects()) + OS << "\"n\")\n"; +else "n" refers to "nothrow" which means the builtin doesn't throw a C++ exception. None of our builtins thr

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

craig.topper updated this revision to Diff 318215. craig.topper added a comment. Herald added a subscriber: hiraditya. Herald added a project: LLVM. Update header on RISCVInstrInfoB.td Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95002/new/ https:

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

craig.topper updated this revision to Diff 318217. craig.topper added a comment. clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94617/new/ https://reviews.llvm.org/D94617 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

craig.topper updated this revision to Diff 318218. craig.topper added a comment. Rebase after clang-format in Zba patch Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95002/new/ https://reviews.llvm.org/D95002 Files: clang/lib/Driver/ToolChains/A

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

craig.topper updated this revision to Diff 318219. craig.topper added a comment. Remove conflict marker that got left behind Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95002/new/ https://reviews.llvm.org/D95002 Files: clang/lib/Driver/ToolCha

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94583/new/ https://reviews.llvm.org/D94583 _

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105690/new/ https://reviews.llvm.org/D105690 ___

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1372 +(VMANDN_MM VR:$vd, VR:$vs2, VR:$vs1), 0>; + +def : InstAlias<"vmornot.mm $vd, $vs2, $vs1", Probably not worth having a blank line between vmandnot and v

[PATCH] D111529: Specify Clang vector builtins.

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:552 +operation(x, y) as pairwise tree reduction to the input. The pairs are formed +by concatenating both inputs and pairing adjacent elements. + I'm not sure I understand what is b

[PATCH] D110779: [RISCV] Require tail policy argument to builtins to be an integer constant expression

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa5c3508ac71b: [RISCV] Require tail policy argument to builtins to be an integer constant… (authored by craig.topper). Herald added a project: clang.

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:194 - if (MArch.startswith_insensitive("rv32")) { -// FIXME: parse `March` to find `D` extension properly -if (MArch.substr(4).contains_insensitive("d") || -MArch.startsw

[PATCH] D110684: [RISCV] Define _m intrinsics as builtins, instead of macros.

craig.topper added a comment. This patch was uploaded without full context. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110684/new/ https://reviews.llvm.org/D110684 ___ cfe-commits mailing list cfe-com

[PATCH] D110684: [RISCV] Define _m intrinsics as builtins, instead of macros.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110684/new/ https://reviews.llvm.org/D110684 ___

[PATCH] D111529: Specify Clang vector builtins.

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:552 +operation(x, y) as pairwise tree reduction to the input. The pairs are formed +by concatenating both inputs and pairing adjacent elements. + fhahn wrote: > craig.topper wrote:

[PATCH] D110684: [RISCV] Define _m intrinsics as builtins, instead of macros.

craig.topper added a comment. In D110684#3059698 , @aeubanks wrote: > In D110684#3057498 , @nikic wrote: > >> I noticed this a few time in the past already, but this is the worst one yet: >> >> Compile-time: >> h

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

craig.topper added a comment. I think this looks good other than the whitespace in fixed-vectors-mask-logic.ll that Jessica commented on. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111062/new/ https://reviews.llvm.org/D111062 _

[PATCH] D111692: [RISCV] Remove Zvamo C intrinsics and builtins.

craig.topper created this revision. craig.topper added reviewers: kito-cheng, HsiangKai, khchen, rogfer01, frasercrmck, arcbbb. Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, t

[PATCH] D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

craig.topper updated this revision to Diff 379276. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110669/new/ https://reviews.llvm.org/D11066

[PATCH] D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

craig.topper updated this revision to Diff 379278. craig.topper added a comment. Add back dropped changes to RISCV.td Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110669/new/ https://reviews.llvm.org/D110669 Files: clang/lib/Basic/Targets/RISCV

[PATCH] D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

craig.topper updated this revision to Diff 379279. craig.topper added a comment. clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110669/new/ https://reviews.llvm.org/D110669 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Driver/

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM other than that comment about removing 'b' from AllStdExts. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:39 + +static constexpr StringLiteral AllStdExts = "

[PATCH] D111755: [ARM] Don't use TARGET_HEADER_BUILTIN in arm_mve_builtins.inc or arm_cde_builtins.inc

craig.topper created this revision. craig.topper added reviewers: simon_tatham, efriedma, miyuki, rnk. Herald added subscribers: dmgreen, kristof.beyls. craig.topper requested review of this revision. Herald added a project: clang. The attributes string doesn't include 'f' or 'h'. I don't think an

[PATCH] D111692: [RISCV] Remove Zvamo C intrinsics and builtins.

craig.topper added a comment. My motivation was to reduce clang binary size by at least 50K and reduce our intrinsic count by 4% while we figure out ways to reduce the RISCV vector intrinsic load on clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D111529: Specify Clang vector builtins.

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:552 +operation(x, y) as pairwise tree reduction to the input. The pairs are formed +by concatenating both inputs and pairing adjacent elements. + fhahn wrote: > craig.topper wrote:

[PATCH] D111778: [WIP][X86] Update CPU_SPECIFIC list.

craig.topper added a comment. In D111778#3064287 , @FreddyYe wrote: > In D111778#3063891 , @erichkeane > wrote: > >> Supporting these types requires changes to the library so that we can check >> these, right?

[PATCH] D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

This revision was automatically updated to reflect the committed changes. Closed by commit rGf7ba572483dd: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D11066

[PATCH] D111778: [WIP][X86] Update CPU_SPECIFIC list.

craig.topper added a comment. In D111778#3064555 , @erichkeane wrote: > In D111778#3064439 , @craig.topper > wrote: > >> In D111778#3064287 , @FreddyYe >> wrote: >> >>>

[PATCH] D111755: [ARM] Don't use TARGET_HEADER_BUILTIN in arm_mve_builtins.inc or arm_cde_builtins.inc

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc294715e2e0c: [ARM] Don't use TARGET_HEADER_BUILTIN in arm_mve_builtins.inc or… (authored by craig.topper). Repository: rG LLVM Github Monorepo C

[PATCH] D111923: [RISCV] Split RISCV vector builtins into their own file and namespace.

craig.topper created this revision. craig.topper added reviewers: HsiangKai, khchen, arcbbb, kito-cheng. Herald added subscribers: achieveartificialintelligence, ctetreau, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, th

[PATCH] D112001: [Clang] Add min/max reduction builtins.

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:16673 + if (!VecTy) + if (!TyA->getAs()) + return Diag(A->getBeginLoc(), diag::err_elementwise_math_invalid_arg_type_2) Is this indented incorrectly? There appear to be 2 ifs

[PATCH] D111986: [Clang] Add elementwise abs builtin.

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:3109 + Result = Builder.CreateBinaryIntrinsic( + llvm::Intrinsic::abs, Op0, Builder.getFalse(), nullptr, "elt.abs"); +else Did we discuss that this is different than

[PATCH] D112020: [RISCV] Use clang_builtin_alias for all RISCV vector intrinsics.

craig.topper created this revision. craig.topper added reviewers: khchen, arcbbb, kito-cheng, HsiangKai, evandro. Herald added subscribers: achieveartificialintelligence, jeroen.dobbelaere, StephenFan, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei,

[PATCH] D111529: Specify Clang vector builtins.

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:557 +``i in [0, Number of elements / 2)``. If the numbers of elements is not a +power of 2, the vector is widening with neutral elements for the reduction +at the end to the next power of 2. ---

[PATCH] D111986: [Clang] Add elementwise abs builtin.

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:3109 + Result = Builder.CreateBinaryIntrinsic( + llvm::Intrinsic::abs, Op0, Builder.getFalse(), nullptr, "elt.abs"); +else craig.topper wrote: > Did we discuss that

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper added a comment. In D105168#3069499 , @teemperor wrote: > This broke the modules build: > > While building module 'LLVM_Utils' imported from > lvm/lib/Support/TargetParser.cpp:14: > In file included from :209: > llvm/include/llvm/Suppo

[PATCH] D112028: [RISCV] Remove the HasSideEffects property from riscv_vector.td

craig.topper created this revision. craig.topper added reviewers: HsiangKai, kito-cheng, arcbbb, khchen. Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruce

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper added a comment. In D105168#3071249 , @jrtc27 wrote: > Two options come to mind if we really need to be outputting a StringRef list: > > 1. (the simpler option) Pass in a Twine -> `const char *` lambda that the > caller hooks up to Args.Make

[PATCH] D112032: [RISCV] Use a lambda to avoid having the Support library depend on Option library.

craig.topper created this revision. craig.topper added reviewers: jrtc27, kito-cheng, HsiangKai, khchen, arcbbb. Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper added a comment. In D105168#3071330 , @jrtc27 wrote: > In D105168#3071321 , @craig.topper > wrote: > >> In D105168#3071249 , @jrtc27 wrote: >> >>> Two option

[PATCH] D112032: [RISCV] Use a lambda to avoid having the Support library depend on Option library.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1053e0b27ce1: [RISCV] Use a lambda to avoid having the Support library depend on Option… (authored by craig.topper). Repository: rG LLVM Github Mo

[PATCH] D111923: [RISCV] Split RISCV vector builtins into their own file and namespace.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG34173330bb3f: [RISCV] Split RISCV vector builtins into their own file and namespace. (authored by craig.topper). Repository: rG LLVM Github Monore

[PATCH] D112028: [RISCV] Remove the HasSideEffects property from riscv_vector.td

This revision was automatically updated to reflect the committed changes. Closed by commit rG39a1fcb9cf59: [RISCV] Remove the HasSideEffects property from riscv_vector.td (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D112028?vs=380496&id=380583#toc Repository:

[PATCH] D111692: [RISCV] Remove Zvamo C intrinsics and builtins.

craig.topper updated this revision to Diff 380587. craig.topper added a comment. Reduce scope since RISCVISAInfo landed. We need more changes to MC tests if we we remove Zvamo from RISCVISAInfo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111692/n

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

craig.topper created this revision. craig.topper added reviewers: khchen, kito-cheng, arcbbb, HsiangKai, evandro, MaskRay, aeubanks, nikic. Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl,

[PATCH] D112020: [RISCV] Use clang_builtin_alias for all RISCV vector intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa29dfc089d18: [RISCV] Use clang_builtin_alias for all RISCV vector intrinsics. (authored by craig.topper). Changed prior to commit: https://review

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