[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

4vtomat updated this revision to Diff 514302. 4vtomat added a comment. Resolved MaskRay's comments. Should we use @Kito's approach to deal with -march=help? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.org/D146054

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 498253. 4vtomat marked 2 inline comments as done. 4vtomat added a comment. Update to v20230206 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141672/new/ https://reviews.llvm.org/D141672 Files: clang/test/Pre

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

4vtomat updated this revision to Diff 520904. 4vtomat added a comment. Remove -march=help alias. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.org/D146054 Files: clang/include/clang/Driver/Options.td clang/incl

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

4vtomat updated this revision to Diff 522411. 4vtomat added a comment. Resolved MaskRay's comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.org/D146054 Files: clang/include/clang/Driver/Options.td clang/i

[PATCH] D148680: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td

4vtomat created this revision. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, ni

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

4vtomat updated this revision to Diff 514810. 4vtomat added a comment. Resolved Kito's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 Files: clang/include/clang/Basic/riscv_sifive_vcix.td cl

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

4vtomat updated this revision to Diff 514812. 4vtomat added a comment. Rename riscv_sifive_vcix.td to riscv_sifive_vector.td Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 Files: clang/include/clang/Ba

[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

4vtomat updated this revision to Diff 514817. 4vtomat added a comment. Resolved Kito's comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148308/new/ https://reviews.llvm.org/D148308 Files: clang/include/clang/Basic/BuiltinsRISCVVector.def

[PATCH] D148680: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td

4vtomat added a comment. In D148680#4279291 , @craig.topper wrote: > Are we running tablegen separately for each vendor extension? Yes, I guess the vendor extensions should be separated into different tablegen file so that they don't be in risv_vector.

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

4vtomat updated this revision to Diff 514821. 4vtomat added a comment. Resolved Craig's comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 Files: clang/include/clang/Basic/riscv_sifive_vector.td

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

4vtomat updated this revision to Diff 516137. 4vtomat added a comment. Resolved Alex's comment. Moved both of extensions to experimental. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148066/new/ https://reviews.llvm.org/D148066 Files: clang/tes

[PATCH] D147935: [RISCV] Add SiFive extension support

This revision was automatically updated to reflect the committed changes. Closed by commit rGcd5c4cb7e0ae: [RISCV] Add SiFive extension support (authored by kito-cheng, committed by 4vtomat). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147935/new/

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

4vtomat updated this revision to Diff 516596. 4vtomat added a comment. Resolved Craig's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 Files: clang/include/clang/Basic/riscv_sifive_vector.td

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

4vtomat updated this revision to Diff 516598. 4vtomat added a comment. Removed unnecessary comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 Files: clang/include/clang/Basic/riscv_sifive_vector.t

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

4vtomat updated this revision to Diff 516708. 4vtomat added a comment. Rename clang/test/Driver/print-supported-marchs.c to clang/test/Driver/print-supported-extensions.c Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.ll

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

4vtomat updated this revision to Diff 517113. 4vtomat added a comment. Update to version 0.5.1. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138810/new/ https://reviews.llvm.org/D138810 Files: clang/include/clang/Basic/riscv_vector.td clang/

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

This revision was automatically updated to reflect the committed changes. Closed by commit rG74c1fa60b5f5: [RISCV] Add Smaia and Ssaia extensions support (authored by 4vtomat). Changed prior to commit: https://reviews.llvm.org/D148066?vs=516137&id=518634#toc Repository: rG LLVM Github Monore

[PATCH] D148223: [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.

This revision was automatically updated to reflect the committed changes. Closed by commit rG8ed9cf06e900: [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension. (authored by Nelson1225, committed by 4vtomat). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://r

[PATCH] D148680: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4bf846ba40f1: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td (authored by 4vtomat). Repository: rG LLVM Github Monorepo CHAN

[PATCH] D148308: [RISCV][RISCV][clang] Split out SiFive VCIX C intrinsics from riscv_vector.td

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGfa43608d1649: [RISCV][RISCV][clang] Split out SiFive Vector C intrinsics from riscv_vector.td (authored by 4vtomat). Changed prior to commit: http

[PATCH] D148223: [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.

4vtomat added a comment. In D148223#4312296 , @TWeaver wrote: > Hello and Good Afternoon from the UK, > > I believe this revision has started the following build bot to start failing > on these 5 tests: > > https://lab.llvm.org/buildbot/#/builders/216/bu

[PATCH] D148223: [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.

4vtomat added a comment. Hi @craig.topper and @kito-cheng , the build error message was: 'z:\test\build\lib\clang\17\include\sifive_vector.h:12:10: fatal error: 'riscv_vector.h' file not found'. Have you ever met this before? I'm not sure if I forgot to add something or not.. Repository: rG

[PATCH] D148223: [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.

4vtomat added a comment. In D148223#4312460 , @4vtomat wrote: > Hi @craig.topper and @kito-cheng , the build error message was: > 'Z:\test\llvm-project\clang\test\CodeGen\RISCV\rvv-intrinsics-autogenerated\non-policy\non-overloaded\xsfvcp-x-rv64.c:4:10:

[PATCH] D148223: [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.

4vtomat added a comment. In D148223#4312515 , @dyung wrote: > In D148223#4312460 , @4vtomat wrote: > >> Hi @craig.topper and @kito-cheng , the build error message was: >> 'Z:\test\llvm-project\clang\test\CodeGen\

[PATCH] D149655: [tests] Add missing REQUIRES: riscv-registered-target to clang test

4vtomat created this revision. Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuas

[PATCH] D149655: [tests] Add missing REQUIRES: riscv-registered-target to clang test

4vtomat closed this revision. 4vtomat added a comment. Merged. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149655/new/ https://reviews.llvm.org/D149655 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

4vtomat added inline comments. Comment at: clang/lib/Driver/Driver.cpp:110 +extern void RISCVMarchHelp(); + craig.topper wrote: > Can we declare this in RISCVISAInfo.h and include that here? Yes, we can. Comment at: clang/tools/driver/cc1_mai

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

4vtomat added a comment. Sorry for late reply, this is the relevant spec for C intrinsics: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234 I will update the patch according to this! Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat added a comment. In D138807#3972441 , @craig.topper wrote: > In D138807#3962417 , @craig.topper > wrote: > >> Anything that uses OP-P needs to have a DecoderNamespace assigned and >> RISCVDisassembler::

[PATCH] D139387: [Clang] Support policy function for all vector segment load.

4vtomat created this revision. Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb. Herald added a project: All. 4vtom

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 480320. 4vtomat added a comment. Resolved Craig's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features.c l

[PATCH] D139387: [Clang] Support policy function for all vector segment load.

4vtomat updated this revision to Diff 480321. 4vtomat added a comment. Resolved Craig's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139387/new/ https://reviews.llvm.org/D139387 Files: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded

[PATCH] D139387: [NFC][Clang] Add missing test cases for segment load

4vtomat updated this revision to Diff 481521. 4vtomat added a comment. Update failed test cases. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139387/new/ https://reviews.llvm.org/D139387 Files: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 481540. 4vtomat added a comment. Address Eric Gouriou's comments, thanks for reviewing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocess

[PATCH] D139387: [NFC][Clang] Add missing test cases for segment load

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4ca9c6a84f91: [NFC][Clang] Add missing test cases for segment load (authored by khchen, committed by 4vtomat). Repository: rG LLVM Github Monorepo

[PATCH] D120967: [NFC] Divide tests into smaller files

4vtomat created this revision. Herald added subscribers: luke957, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb. Herald added a project:

[PATCH] D120967: [NFC] Divide tests into smaller files

4vtomat added a comment. In D120967#3359188 , @kito-cheng wrote: > LGTM, but do you mind give more comment on SUMMARY to describe what you did? You are right lol. I've added some~ Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION http

[PATCH] D120967: [NFC] Divide tests into smaller files

This revision was automatically updated to reflect the committed changes. Closed by commit rG5a148869d336: [NFC] Divide tests into smaller files (authored by 4vtomat). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120967/new/ https://reviews.llvm.or

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