jhuber6 wrote:
> First I will always consider NVVM reflect a giant hack. NVVM reflect cannot
> actually deal with the full range of wavesize issues. It is an incompatible
> ABI and the code should never be intermixed
It's a hack, but still better than whatever it is AMD does currently.
https:
arsenm wrote:
> > This probably should retain separate wave32/wave64 builds. Additionally,
> > should have extension points for subtarget specific implementations
>
> That's what Shilei was talking about since we have `__nvvm_reflect` for that
> for NVPTX.
First I will always consider NVVM re
shiltian wrote:
> This probably should retain separate wave32/wave64 builds. Additionally,
> should have extension points for subtarget specific implementations
Does wave32/wave64 affect the lowering from front end source code to middle end
IR, if we don't use certain functions, such as wave l
@@ -288,18 +258,11 @@ function(compileDeviceRTLLibrary target_cpu target_name
target_triple)
endif()
endfunction()
-# Generate a Bitcode library for all the gpu architectures the user requested.
-add_custom_target(omptarget.devicertl.nvptx)
add_custom_target(omptarget.devi
https://github.com/c8ef updated https://github.com/llvm/llvm-project/pull/119082
>From 2af0eb663a106b712a3c9eb2028dc35014884708 Mon Sep 17 00:00:00 2001
From: c8ef
Date: Sun, 8 Dec 2024 01:11:51 +0800
Subject: [PATCH 1/4] constexpr elementwise add_sat
---
clang/docs/LanguageExtensions.rst
arsenm wrote:
> Two, we can add a "readnone_fp_intrinsic" attribute, which would mean the
> intrinsic is readnone unless there's an operand bundle indicating otherwise.
I think this needs to be more refined to FP mode read/write and errno
read/write. Basically a mirror of memory() for argument
https://github.com/RKSimon approved this pull request.
LGTM cheers
https://github.com/llvm/llvm-project/pull/119082
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@@ -288,18 +258,11 @@ function(compileDeviceRTLLibrary target_cpu target_name
target_triple)
endif()
endfunction()
-# Generate a Bitcode library for all the gpu architectures the user requested.
-add_custom_target(omptarget.devicertl.nvptx)
add_custom_target(omptarget.devi
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/119082
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kovdan01 wrote:
@MaskRay Please let me know if latest changes fix your previous comments and if
this could be merged.
https://github.com/llvm/llvm-project/pull/113148
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@@ -822,3 +822,19 @@ static_assert(__builtin_elementwise_bitreverse(0x12345678)
== 0x1E6A2C48);
static_assert(__builtin_elementwise_bitreverse(0x0123456789ABCDEFULL) ==
0xF7B3D591E6A2C480);
static_assert(__builtin_bit_cast(unsigned,
__builtin_elementwise_bitreverse((vector4ch
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/119082
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jhuber6 wrote:
> This probably should retain separate wave32/wave64 builds. Additionally,
> should have extension points for subtarget specific implementations
That's what Shilei was talking about since we have `__nvvm_reflect` for that
for NVPTX.
https://github.com/llvm/llvm-project/pull/119
arsenm wrote:
This probably should retain separate wave32/wave64 builds. Additionally, should
have extension points for subtarget specific implementations
https://github.com/llvm/llvm-project/pull/119091
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@@ -178,6 +266,9 @@ void SPIRVPassConfig::addIRPasses() {
addPass(createSPIRVStructurizerPass());
}
+ if (TM.getOptLevel() > CodeGenOptLevel::None)
+addPass(createInferAddressSpacesPass(AddressSpace::Generic));
arsenm wrote:
I remember we had some
@@ -92,6 +98,65 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -92,6 +98,65 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
https://github.com/cor3ntin approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/119024
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