@@ -1780,6 +1780,14 @@ class TargetInfo : public TransferrableTargetInfo,
return 0;
}
+ /// \returns Target specific address space for indirect (e.g. sret)
arguments.
+ /// If such an address space exists, it must be convertible to and from the
+ /// alloca address s
alexfh wrote:
Sorry, we've been in a bit of a firefighting. I'll try to arrange some time for
this till the EOW.
https://github.com/llvm/llvm-project/pull/111992
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@@ -156,6 +157,8 @@ StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK)
{
switch (AK) {
case AMDGPU::GK_GFX9_GENERIC:
return "gfx9";
+ case AMDGPU::GK_GFX9_4_GENERIC:
+return "gfx9";
arsenm wrote:
What is this used for? I'm not sure how t
@@ -5,17 +5,22 @@
StructuredBuffer Buf : register(t10);
RWStructuredBuffer Buf2 : register(u5, space1);
+RasterizerOrderedStructuredBuffer Buf5 : register(u1, space2);
// CHECK: %"class.hlsl::StructuredBuffer" = type { target("dx.RawBuffer",
float, 0, 0), float }
// CHECK
Author: Helena Kotas
Date: 2024-11-06T10:28:04-08:00
New Revision: 39f2bae2407e08176a453c7c7e6f4888bbf28a4e
URL:
https://github.com/llvm/llvm-project/commit/39f2bae2407e08176a453c7c7e6f4888bbf28a4e
DIFF:
https://github.com/llvm/llvm-project/commit/39f2bae2407e08176a453c7c7e6f4888bbf28a4e.diff
https://github.com/hekota closed
https://github.com/llvm/llvm-project/pull/113648
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@@ -942,7 +942,13 @@ uint64_t dot(uint64_t4, uint64_t4);
_HLSL_AVAILABILITY(shadermodel, 6.4)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot4add_i8packed)
-int dot4add_i8packed(unsigned int, unsigned int, int);
+int dot4add_i8packed(uint, uint, int);
inbelic wrote:
S
@@ -0,0 +1,65 @@
+; RUN: llc -O0 -mtriple=spirv1.5-unknown-unknown %s -o - | FileCheck %s
--check-prefixes=CHECK,CHECK-EXP
+; RUN: llc -O0 -mtriple=spirv1.6-unknown-unknown %s -o - | FileCheck %s
--check-prefixes=CHECK,CHECK-DOT
+; RUN: llc -O0 -mtriple=spirv-unknown-unknown
-s
inbelic wrote:
> I didn't see `SemaHLSL.cpp` changes, I saw the tests though.
Since the function signature is completely captured in `hlsl_intrinsics.h` we
aren't required to manually define it in `SemaHLSL.cpp`
https://github.com/llvm/llvm-project/pull/115068
_
https://github.com/a-tarasyuk updated
https://github.com/llvm/llvm-project/pull/113777
>From 78019b9d9dc138f38bb5b32576b621351ae6427c Mon Sep 17 00:00:00 2001
From: Oleksandr T
Date: Sun, 27 Oct 2024 01:07:57 +0300
Subject: [PATCH 1/6] [Clang] prevent assertion failure from an invalid
template
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/115068
>From 414b07fd2276946936dc137fb633b04cd8c12fc4 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Tue, 5 Nov 2024 21:15:17 +
Subject: [PATCH 1/4] [HLSL][SPIRV][DXIL] Implement `dot4add_u8packed`
intrinsic
-
https://github.com/a-tarasyuk updated
https://github.com/llvm/llvm-project/pull/113777
>From 78019b9d9dc138f38bb5b32576b621351ae6427c Mon Sep 17 00:00:00 2001
From: Oleksandr T
Date: Sun, 27 Oct 2024 01:07:57 +0300
Subject: [PATCH 1/6] [Clang] prevent assertion failure from an invalid
template
https://github.com/efriedma-quic updated
https://github.com/llvm/llvm-project/pull/113506
>From 5d789d1698070d12d3c64e58cf1cd04624becce7 Mon Sep 17 00:00:00 2001
From: Eli Friedman
Date: Wed, 23 Oct 2024 16:12:27 -0700
Subject: [PATCH] [clang codegen] Add CreateRuntimeFunction overload that tak
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Eli Friedman (efriedma-quic)
Changes
Correctly computing the LLVM types/attributes is complicated in general, so add
a variant which does that for you.
---
Full diff: https://github.com/llvm/llvm-project/pull/113506.diff
4 Files
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Eli Friedman (efriedma-quic)
Changes
Correctly computing the LLVM types/attributes is complicated in general, so add
a variant which does that for you.
---
Full diff: https://github.com/llvm/llvm-project/pull/113506.diff
4 Files Affecte
https://github.com/Michael137 edited
https://github.com/llvm/llvm-project/pull/115245
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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/Michael137 edited
https://github.com/llvm/llvm-project/pull/115245
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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -462,6 +462,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final :
public TargetInfo {
}
bool hasHIPImageSupport() const override { return HasImage; }
+
+ std::pair hardwareInterferenceSizes() const override {
+return std::make_pair(128, 128);
--
https://github.com/ppenzin updated
https://github.com/llvm/llvm-project/pull/115100
>From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001
From: Petr Penzin
Date: Tue, 5 Nov 2024 13:11:48 -0600
Subject: [PATCH 1/2] [RISCV] Add TT-Ascalon-d8 processor
Ascalon is an out-of-order
https://github.com/jhuber6 updated
https://github.com/llvm/llvm-project/pull/115241
>From fcb8bcfba329b6ad9f33ace70c22ca4b542d2117 Mon Sep 17 00:00:00 2001
From: Joseph Huber
Date: Wed, 6 Nov 2024 18:27:07 -0600
Subject: [PATCH 1/2] [AMDGPU] Make `__GCC_DESTRUCTIVE_SIZE` 128 on AMDGPU
Summary:
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/zygoloid closed
https://github.com/llvm/llvm-project/pull/114857
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Author: Richard Smith
Date: 2024-11-06T18:45:27-08:00
New Revision: de18fa1ace1cd717da9482a09d0a0db8666f48b7
URL:
https://github.com/llvm/llvm-project/commit/de18fa1ace1cd717da9482a09d0a0db8666f48b7
DIFF:
https://github.com/llvm/llvm-project/commit/de18fa1ace1cd717da9482a09d0a0db8666f48b7.diff
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