Author: antangelo
Date: 2024-01-16T21:06:02-05:00
New Revision: 46a395d8c41f6009a7fbae51f408c3c6ea2399d3
URL:
https://github.com/llvm/llvm-project/commit/46a395d8c41f6009a7fbae51f408c3c6ea2399d3
DIFF:
https://github.com/llvm/llvm-project/commit/46a395d8c41f6009a7fbae51f408c3c6ea2399d3.diff
LOG
https://github.com/antangelo closed
https://github.com/llvm/llvm-project/pull/78083
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https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/8] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
@@ -57,11 +57,16 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
@@ -151,9 +157,12 @@ Usage
To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
to both compile and link command lines. On aarch64, you also need to pass
-``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3``
-(``gp``) is alwa
@@ -27,6 +27,11 @@
// DEFAULT-NOT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mforced-sw-shadow-stack
2>&1 | FileCheck %s -check-prefix=FORCE-SW-SCS
yetingk wrote:
@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension tar
@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension tar
@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension tar
glandium wrote:
> It looks like this breaks building at least `MultiSource` from
> https://github.com/llvm/llvm-test-suite/. The first failure I see is when
> building `llvm-test-suite/MultiSource/Applications/ClamAV/zlib_zutil.c`
>
> ```
> In file included from
> /llvm-test-suite/MultiSource
@@ -722,6 +709,12 @@ struct MCDCCoverageBuilder {
return I->second;
}
+ /// Return the LHS Decision ({0,0} if not set).
+ const DecisionIDPair &back() {
+assert(DecisionStack.size() >= 1);
ornata wrote:
This assert should be unnecessary. `SmallV
@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
return E->getOpcode() == BO_LAnd;
}
- /// Push an ID onto the corresponding RHS stack.
- void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector &rhs = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[Code
@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
return E->getOpcode() == BO_LAnd;
}
- /// Push an ID onto the corresponding RHS stack.
- void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector &rhs = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[Code
@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
#endif /* __x86_64__ */
#ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the \
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/77686
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@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
return E->getOpcode() == BO_LAnd;
}
- /// Push an ID onto the corresponding RHS stack.
- void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector &rhs = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[Code
Author: Phoebe Wang
Date: 2024-01-17T11:40:32+08:00
New Revision: 8d6e82d501cda1946c7d99658241033d78676e95
URL:
https://github.com/llvm/llvm-project/commit/8d6e82d501cda1946c7d99658241033d78676e95
DIFF:
https://github.com/llvm/llvm-project/commit/8d6e82d501cda1946c7d99658241033d78676e95.diff
L
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/77733
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phoebewang wrote:
Thanks @KanRobert !
https://github.com/llvm/llvm-project/pull/77733
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https://github.com/antangelo created
https://github.com/llvm/llvm-project/pull/78387
Use the template pattern in determining whether to synthesize the aggregate
deduction guide, and update DeclareImplicitDeductionGuideFromInitList to
substitute outer template arguments.
Fixes #77599
>From 50
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (antangelo)
Changes
Use the template pattern in determining whether to synthesize the aggregate
deduction guide, and update DeclareImplicitDeductionGuideFromInitList to
substitute outer template arguments.
Fixes #77599
---
Full dif
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/3] [RISCV] Overwrite cpu target features for full arch
string in targ
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/78384
>From 04bbfad594054c2dab033b977c7dfa178fee8568 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Thu, 4 Jan 2024 21:00:23 +0800
Subject: [PATCH 1/2] [X86] Support "f16c" and "avx512fp16" for
__builtin_cpu_suppor
@@ -184,12 +185,12 @@ X86_FEATURE (AMX_TILE,"amx-tile")
X86_FEATURE (CLDEMOTE,"cldemote")
X86_FEATURE (CLFLUSHOPT, "clflushopt")
X86_FEATURE (CLWB,"clwb")
+X86_FEATURE_COMPAT(F16C,"f16c", 38)
https://github.com/FreddyLeaf deleted
https://github.com/llvm/llvm-project/pull/78384
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CoTinker wrote:
I've revised it. Can you check it again? @phoebewang
https://github.com/llvm/llvm-project/pull/77907
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brad0 wrote:
There is a conflict at the moment. Also 18 is coming up.
https://github.com/llvm/llvm-project/pull/74927
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compnerd wrote:
Thank you for fixing the documentation!
https://github.com/llvm/llvm-project/pull/76418
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Author: h-vetinari
Date: 2024-01-16T20:28:29-08:00
New Revision: 3e0d71cdf4a406c6a1de825cf69d889d97ede46b
URL:
https://github.com/llvm/llvm-project/commit/3e0d71cdf4a406c6a1de825cf69d889d97ede46b
DIFF:
https://github.com/llvm/llvm-project/commit/3e0d71cdf4a406c6a1de825cf69d889d97ede46b.diff
LO
https://github.com/compnerd closed
https://github.com/llvm/llvm-project/pull/76418
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@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension tar
https://github.com/JDevlieghere created
https://github.com/llvm/llvm-project/pull/78392
Upstream XROS support in the clang frontend and driver.
>From 1e65420f87eed1f7f4380496f96eef2560a15cb0 Mon Sep 17 00:00:00 2001
From: Jonas Devlieghere
Date: Tue, 16 Jan 2024 20:36:47 -0800
Subject: [PATCH]
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Jonas Devlieghere (JDevlieghere)
Changes
Upstream XROS support in the clang frontend and driver.
---
Full diff: https://github.com/llvm/llvm-project/pull/78392.diff
10 Files Affected:
- (modified) clang/lib/Basic/Targets/OSTargets.h (+5
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-clang-codegen
Author: Jonas Devlieghere (JDevlieghere)
Changes
Upstream XROS support in the clang frontend and driver.
---
Full diff: https://github.com/llvm/llvm-project/pull/78392.diff
10 Files Affected:
- (modi
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension tar
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/4] [RISCV] Overwrite cpu target features for full arch
string in targ
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?=
Message-ID:
In-Reply-To:
https://github.com/tbaederr updated
https://github.com/llvm/llvm-project/pull/69900
>From 58ff884a20816526ea1b3e4035a65ab435e2396d Mon Sep 17 00:00:00 2001
From: =?UTF-8?
@@ -80,6 +80,11 @@ static cl::opt EnableRISCVDeadRegisterElimination(
" them with stores to x0"),
cl::init(true));
+// TODO: This should be controlled by -mtls-dialect=
+cl::opt EnableRISCVTLSDESC("riscv-enable-tlsdesc",
MaskRay wrote:
We sho
https://github.com/jcsxky updated
https://github.com/llvm/llvm-project/pull/78088
>From 55b433e5bad38b2ce359c480066b1b8c2917ebbf Mon Sep 17 00:00:00 2001
From: huqizhi
Date: Sun, 14 Jan 2024 15:07:26 +0800
Subject: [PATCH] [Clang][Sema] fix crash of attribute transform
---
clang/include/clang
https://github.com/MaskRay approved this pull request.
LGTM once the TLSDESC option is moved to use llvm/lib/CodeGen/CommandFlags.cpp
It's worth giving others some time to respond.
https://github.com/llvm/llvm-project/pull/66915
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@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+template
+struct Bar {
+int* data;
+
+auto operator[](const int index) const [[clang::lifetimebound]] ->
decltype(data[index]) {
+return data[index];
+}
+};
+
+int m
https://github.com/MaskRay edited
https://github.com/llvm/llvm-project/pull/66915
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https://github.com/Long5hot updated
https://github.com/llvm/llvm-project/pull/77732
>From ec05087b89af829247879c2e860f9d93f548c7a1 Mon Sep 17 00:00:00 2001
From: Kishan Parmar
Date: Wed, 17 Jan 2024 10:29:34 +0530
Subject: [PATCH] [clang][PowerPC] Add flag to enable compatibility with GNU
for
@@ -162,6 +162,19 @@ class OffloadFile : public OwningBinary {
std::unique_ptr Buffer)
: OwningBinary(std::move(Binary), std::move(Buffer)) {}
+ /// Make a deep copy of this offloading file.
+ OffloadFile copy() const {
+std::unique_ptr Buffer = Memor
https://github.com/jcsxky updated
https://github.com/llvm/llvm-project/pull/77727
>From 67396b51f45f36391bbcf47d1d4cae9274d18526 Mon Sep 17 00:00:00 2001
From: huqizhi
Date: Thu, 11 Jan 2024 13:02:21 +0800
Subject: [PATCH] [Clang][SemaCXX] improve sema check of clang::musttail
attribute
---
https://github.com/cor3ntin closed
https://github.com/llvm/llvm-project/pull/78195
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Author: cor3ntin
Date: 2024-01-17T06:16:12+01:00
New Revision: 4e64159c866446ed7f5783649f8f5699f84bb1a6
URL:
https://github.com/llvm/llvm-project/commit/4e64159c866446ed7f5783649f8f5699f84bb1a6
DIFF:
https://github.com/llvm/llvm-project/commit/4e64159c866446ed7f5783649f8f5699f84bb1a6.diff
LOG:
felix642 wrote:
@11happy what are you trying to achieve exactly and what is not working ?
Is this related to the example that you provided above?
>```
>auto lhsVar1Str = Lexer::getSourceText(
>>CharSourceRange::getTokenRange(Source.getSpellingLoc(lhsVar1->getBeginLoc()),Source.getSpellingLoc
https://github.com/ampandey-1995 updated
https://github.com/llvm/llvm-project/pull/78242
>From fe6d4abebb12e063e10b2266f76ff1a604783c0c Mon Sep 17 00:00:00 2001
From: Amit Pandey
Date: Mon, 11 Dec 2023 14:23:44 +0530
Subject: [PATCH] [ASan][AMDGPU] Fix Assertion Failure.
Assertion failure `(i
@@ -0,0 +1,48 @@
+;RUN: opt < %s -passes=asan -S | FileCheck %s
+
+target datalayout =
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-
https://github.com/cyndyishida approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/78392
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https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/74537
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@@ -707,7 +723,40 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
(TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) {
// MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS
// written can be accessed. A load from LDS to VMEM
https://github.com/arsenm approved this pull request.
lgtm, but can still fix the -O0 thing
https://github.com/llvm/llvm-project/pull/74537
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@@ -130,6 +130,8 @@
; GCN-O0-NEXT:MachineDominator Tree Construction
; GCN-O0-NEXT:Machine Natural Loop Construction
; GCN-O0-NEXT:MachinePostDominator Tree Construction
+; GCN-O0-NEXT:Basic Alias Analysis (stateless AA impl)
+; GCN-O0-NEXT:
https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/77426
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phoebewang wrote:
> I've revised it. Can you check it again? @phoebewang
I'm not sure the usage of the `isEmptyRecord`. Tagging @asb who modified the
interface recently.
https://github.com/llvm/llvm-project/pull/77907
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robincaloudis wrote:
@jrtc27, I do not have write access. All checks passed. Can you merge the PR?
Thanks.
https://github.com/llvm/llvm-project/pull/71313
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@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
#endif /* __x86_64__ */
#ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the \
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/78384
>From 04bbfad594054c2dab033b977c7dfa178fee8568 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Thu, 4 Jan 2024 21:00:23 +0800
Subject: [PATCH 1/4] [X86] Support "f16c" and "avx512fp16" for
__builtin_cpu_suppor
@@ -437,6 +442,16 @@ namespace {
MostDerivedArraySize = 2;
MostDerivedPathLength = Entries.size();
}
+void addVectorUnchecked(QualType EltTy, uint64_t Size, uint64_t Idx) {
+ Entries.push_back(PathEntry::ArrayIndex(Idx));
+
+ // This is technically
@@ -229,9 +230,9 @@ X86_FEATURE (XSAVE, "xsave")
X86_FEATURE (XSAVEC, "xsavec")
X86_FEATURE (XSAVEOPT,"xsaveopt")
X86_FEATURE (XSAVES, "xsaves")
+X86_FEATURE_COMPAT(AVX512FP16, "avx512fp16",39)
---
@@ -730,68 +723,70 @@ struct MCDCCoverageBuilder {
return;
// If binary expression is disqualified, don't do mapping.
-if (NestLevel.empty() &&
-!MCDCBitmapMap.contains(CodeGenFunction::stripCond(E)))
+if (!isBuilding() &&
!MCDCBitmapMap.contains(Cod
@@ -1847,30 +1850,18 @@ struct CounterCoverageMappingBuilder
// Extract the Parent Region Counter.
Counter ParentCnt = getRegion().getCounter();
-// Extract the MCDC condition IDs (returns 0 if not needed).
-MCDCConditionID NextOrID = MCDCBuilder.getNextLOrCond
@@ -730,68 +723,70 @@ struct MCDCCoverageBuilder {
return;
// If binary expression is disqualified, don't do mapping.
-if (NestLevel.empty() &&
-!MCDCBitmapMap.contains(CodeGenFunction::stripCond(E)))
+if (!isBuilding() &&
!MCDCBitmapMap.contains(Cod
@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
return E->getOpcode() == BO_LAnd;
}
- /// Push an ID onto the corresponding RHS stack.
- void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector &rhs = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[Code
@@ -663,9 +663,12 @@ struct MCDCCoverageBuilder {
private:
CodeGenModule &CGM;
- llvm::SmallVector AndRHS;
- llvm::SmallVector OrRHS;
- llvm::SmallVector NestLevel;
+ struct DecisionIDPair {
+MCDCConditionID TrueID = 0;
+MCDCConditionID FalseID = 0;
+ };
+
+ ll
@@ -1822,20 +1817,28 @@ struct CounterCoverageMappingBuilder
}
void VisitBinLAnd(const BinaryOperator *E) {
-// Keep track of Binary Operator and assign MCDC condition IDs
+bool IsRootNode = MCDCBuilder.isIdle();
+
+// Keep track of Binary Operator and assign M
@@ -1847,30 +1850,18 @@ struct CounterCoverageMappingBuilder
// Extract the Parent Region Counter.
Counter ParentCnt = getRegion().getCounter();
-// Extract the MCDC condition IDs (returns 0 if not needed).
-MCDCConditionID NextOrID = MCDCBuilder.getNextLOrCond
mordante wrote:
> LGTM.
>
> We need to delete
> `clang/test/Driver/Inputs/cxx23_modules/usr/lib/x86_64-linux-gnu/libc++.so`
> and
> `clang/test/Driver/Inputs/cxx23_modules/usr/lib/x86_64-linux-gnu/modules.json`,
> we should generate them with `split-file`
Are you sure that is the proper way
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/76224
>From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001
From: Vang Thao
Date: Thu, 21 Dec 2023 11:58:47 +0100
Subject: [PATCH 1/5] [AMDGPU][GFX12] Add Atomic cond_sub_u32
---
llvm/
@@ -1182,6 +1182,11 @@ The AMDGPU backend implements the following LLVM IR
intrinsics.
The iglp_opt strategy
implementations are subject to change.
+ llvm.atomic.cond.sub.u32 Provides direct access
https://github.com/Endilll approved this pull request.
LGTM. I believe we can go ahead with this even if discussion about raising
minimum Python version is not going anywhere. Better test 3.7 and 3.11 than
just 3.11 anyway.
https://github.com/llvm/llvm-project/pull/77219
__
@@ -1182,6 +1182,11 @@ The AMDGPU backend implements the following LLVM IR
intrinsics.
The iglp_opt strategy
implementations are subject to change.
+ llvm.atomic.cond.sub.u32 Provides direct access
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/76224
>From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001
From: Vang Thao
Date: Thu, 21 Dec 2023 11:58:47 +0100
Subject: [PATCH 1/6] [AMDGPU][GFX12] Add Atomic cond_sub_u32
---
llvm/
@@ -423,6 +423,67 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi",
"n", "gfx12-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts")
+//===---
https://github.com/frederick-vs-ja commented:
It seems that more things are being done #68485. Have you double checked that
PR?
https://github.com/llvm/llvm-project/pull/78356
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https://github.com/frederick-vs-ja edited
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@@ -635,16 +635,16 @@ def execute_command(self) -> bool:
"""
This function reads lines from STDIN and executes the first command
that it finds. The 2 supported commands are:
-/cherry-pick commit0 <...>
asl wrote:
You certainl
@@ -9,7 +9,7 @@
/// \file
/// Defines the Diagnostic-related interfaces.
//
-//===--===//
+//===--===//]
asl wrote:
still un
@@ -598,3 +600,27 @@ namespace B {
}
void g(B::X x) { A::f(x); }
}
+
+namespace static_operator {
+#if __cplusplus >= 201703L
frederick-vs-ja wrote:
Why C++17?
https://github.com/llvm/llvm-project/pull/78356
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cfe
@@ -7081,10 +7085,10 @@ QualType
TreeTransform::TransformAttributedType(
// FIXME: dependent operand expressions?
if (getDerived().AlwaysRebuild() ||
modifiedType != oldType->getModifiedType()) {
-// TODO: this is really lame; we should really be rebuilding the
-
cor3ntin wrote:
@MitalAshok You want to review this?
https://github.com/llvm/llvm-project/pull/76976
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Author: Fangrui Song
Date: 2024-01-16T23:57:42-08:00
New Revision: d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7
URL:
https://github.com/llvm/llvm-project/commit/d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7
DIFF:
https://github.com/llvm/llvm-project/commit/d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7.diff
https://github.com/MaskRay closed
https://github.com/llvm/llvm-project/pull/77886
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https://github.com/MaskRay edited
https://github.com/llvm/llvm-project/pull/77886
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