@@ -56,10 +56,10 @@ namespace Foo = A::B; // namespace alias
using Foo::myfunc; // using declaration
-using namespace Foo;// using directive
+//removing namespace foo; for quality naming
Michael137 wrote:
The `using` directive was used here to ma
minglotus-6 wrote:
> . For IR PGO, there is basically no need to do so as the instrumentation and
> profile-use should be in-sync. For front-end instrumentation, there seem to
> be some use cases to use out of sync profile: https://reviews.llvm.org/D51240.
Thanks for double checking. I noticed
https://github.com/Endilll closed
https://github.com/llvm/llvm-project/pull/74767
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https://github.com/karka228 updated
https://github.com/llvm/llvm-project/pull/74440
>From a80bf9d03f19d48c0aca4af7758dc49516da8825 Mon Sep 17 00:00:00 2001
From: Karl-Johan Karlsson
Date: Tue, 5 Dec 2023 10:03:00 +0100
Subject: [PATCH 1/4] [Sema] Implement support for -Wformat-signedness
In gc
https://github.com/OutOfCache updated
https://github.com/llvm/llvm-project/pull/74471
>From 94ed734c0d8864a08e3b77600dda811040270bd9 Mon Sep 17 00:00:00 2001
From: Jessica Del
Date: Tue, 5 Dec 2023 13:45:58 +0100
Subject: [PATCH 1/5] [AMDGPU] - Add address space for strided buffers
This is an
@@ -56,10 +56,10 @@ namespace Foo = A::B; // namespace alias
using Foo::myfunc; // using declaration
-using namespace Foo;// using directive
+//removing namespace foo; for quality naming
jeevanghimire wrote:
but it can create confusion if we just
@@ -2822,13 +2825,18 @@ bool UnwindCursor::setInfoForSigReturn(Registers_s390x &) {
// onto the stack.
const pint_t pc = static_cast(this->getReg(UNW_REG_IP));
// The PC might contain an invalid address if the unwind info is bad, so
- // directly accessing it could cause
@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b",
MergeNone, "", [IsTupleSet
def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "",
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
}
+let TargetGuard = "sve2p1" in {
+ def SVGET_2_B : SInst
@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
di
@@ -1375,6 +1381,12 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
"__nodebug__, __overloadable__))\n\n";
+ OS << "#ifdef __ARM_FEATURE_SME\n";
+ OS << "#define __asc __attribute__((arm
@@ -20,3 +21,23 @@ int16x8_t incompat_neon_smc(int16x8_t splat)
__arm_streaming_compatible {
// expected-warning@+1 {{builtin call has undefined behaviour when called
from a streaming compatible function}}
return (int16x8_t)__builtin_neon_vqaddq_v((int8x16_t)splat,
(int8x
@@ -500,6 +506,12 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper
&Records) {
case GenArmSmeRangeChecks:
EmitSmeRangeChecks(Records, OS);
break;
+ case GenArmSmeStreamingAttrs:
sdesmalen-arm wrote:
We also need to do this for SVE (you seem
@@ -3058,6 +3058,11 @@ bool Sema::ParseSVEImmChecks(
if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 7))
HasError = true;
break;
+case SVETypeFlags::ImmCheck2_4_Mul2:
sdesmalen-arm wrote:
This shouldn't have moved.
https://github.c
@@ -6,20 +6,21 @@
#include
__attribute__((target("sme")))
-void test_sme(svbool_t pg, void *ptr) {
+void test_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
svld1_hor_za8(0, 0, pg, ptr);
}
__attribute__((target("arch=armv8-a+sme")))
-void test_arch_sme(s
@@ -18,7 +18,7 @@
// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
// CHECK-CXX-NEXT:ret void
//
-void test_svzero_mask_za() {
+__arm_new_za void test_svzero_mask_za() {
sdesmalen-arm wrote:
Why are these `__arm_new_za` rather than `__arm
@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
di
https://github.com/vpykhtin updated
https://github.com/llvm/llvm-project/pull/71556
>From b6204d32554f082821da100043bf872b62f1740b Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH] add instcombine rule
---
clang/test/CodeGenOpenCL/builtins-am
bjosv wrote:
Thanks for the informative review comments @PiotrZSL, much appreciated.
https://github.com/llvm/llvm-project/pull/73119
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https://github.com/jacquesguan updated
https://github.com/llvm/llvm-project/pull/73489
>From dcc71641695128e117b290cd1e63879e0beeb796 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN
Date: Mon, 27 Nov 2023 16:14:04 +0800
Subject: [PATCH] [clang][RISCV] Change default abi with f extension but
witho
jacquesguan wrote:
> I think the conclusion from the LLVM sync-up call was that everyone happy to
> move in this direction, so please add the release note and we can do a final
> review. Thanks!
Done, added release note.
https://github.com/llvm/llvm-project/pull/73489
https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/74594
>From 037dd51fd05ccd70f10dbf4ca75dd1f45e6548c4 Mon Sep 17 00:00:00 2001
From: Caroline Concatto
Date: Wed, 6 Dec 2023 14:02:23 +
Subject: [PATCH 1/2] [Clang][SVE2p1]Add svboolx2 and svboolx4 types fo
CarolineConcatto wrote:
I added the tests for svget and svset. I am not sure about the flag yet.
https://github.com/llvm/llvm-project/pull/74594
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https://github.com/DominikAdamski updated
https://github.com/llvm/llvm-project/pull/73944
>From 60ceda3d1025891f5037f020a2efe35108f62ca3 Mon Sep 17 00:00:00 2001
From: Dominik Adamski
Date: Thu, 30 Nov 2023 08:06:12 -0600
Subject: [PATCH 1/4] [NFC][AMDGPU] Move address space enum to LLVM direct
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff a4e1aa256b14d74da47fdfeb245930a520f5fd64
82ec7a5c59e0e6dbc28a18febc3bb19872616e3b --
rj-jesus wrote:
> The solution is to add `-fno-fortran-main` to the linker options via
> `CMAKE_SHARED_LINKER_FLAGS`. This will need PR #74139 land first. But this
> option will be a good way to control if the flang compiler should attempt
> linking in the `main` stub from its library.
>
> It
https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/73258
>From e0f245e8d6a395afac5de471b55358c7b730a170 Mon Sep 17 00:00:00 2001
From: Caroline Concatto
Date: Wed, 22 Nov 2023 10:03:50 +
Subject: [PATCH 1/6] [Clang][AArch64] Add fix vector types to header
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/74822
Cortex-M52 is an Armv8.1 AArch32 CPU.
Technical specifications available at:
https://developer.arm.com/processors/cortex-m52
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jon
https://github.com/DominikAdamski updated
https://github.com/llvm/llvm-project/pull/73944
>From 60ceda3d1025891f5037f020a2efe35108f62ca3 Mon Sep 17 00:00:00 2001
From: Dominik Adamski
Date: Thu, 30 Nov 2023 08:06:12 -0600
Subject: [PATCH 1/4] [NFC][AMDGPU] Move address space enum to LLVM direct
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-backend-arm
Author: Jonathan Thackray (jthackray)
Changes
Cortex-M52 is an Armv8.1 AArch32 CPU.
Technical specifications available at:
https://developer.arm.com/processors/cortex-m52
---
Full diff: https://github.co
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Jonathan Thackray (jthackray)
Changes
Cortex-M52 is an Armv8.1 AArch32 CPU.
Technical specifications available at:
https://developer.arm.com/processors/cortex-m52
---
Full diff: https://github.com/llvm/llvm-project/pull/74822.diff
11
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff ea85345eb69f751fdfd793016c854605f14f9dfc
5925f180b6a8623ae1f1497f89c1f6ef35517e4a --
https://github.com/kmclaughlin-arm edited
https://github.com/llvm/llvm-project/pull/74594
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@@ -167,3 +167,23 @@ void test_svpmov_lane(){
zn_u32 = svpmov_lane_u32_m(zn_u32, pn, 5); // expected-error {{argument
value 5 is outside the valid range [1, 3]}}
zn_u64 = svpmov_lane_u64_m(zn_u64, pn, 8); // expected-error {{argument
value 8 is outside the valid range [1,
@@ -167,3 +167,23 @@ void test_svpmov_lane(){
zn_u32 = svpmov_lane_u32_m(zn_u32, pn, 5); // expected-error {{argument
value 5 is outside the valid range [1, 3]}}
zn_u64 = svpmov_lane_u64_m(zn_u64, pn, 8); // expected-error {{argument
value 8 is outside the valid range [1,
https://github.com/kmclaughlin-arm commented:
Thank you for adding the tests @CarolineConcatto!
https://github.com/llvm/llvm-project/pull/74594
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@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b",
MergeNone, "", [IsTupleSet
def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "",
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
}
+let TargetGuard = "sve2p1" in {
+ def SVGET_2_B : SInst
DavidSpickett wrote:
I also made a small change in this area the other day and got a mountain of
clang-format-diff changes.
So in case it's not clear, you can ignore the formatter and it won't block the
approval/merge. Makes sense not to fill the change with unrelated formatting
changes.
htt
@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
* Implemented :ref:`llvm.get.rounding `
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.
DavidSpickett wrote:
Thi
@@ -3058,6 +3058,11 @@ bool Sema::ParseSVEImmChecks(
if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 7))
HasError = true;
break;
+case SVETypeFlags::ImmCheck2_4_Mul2:
SamTebbs33 wrote:
I think you were looking at an old commit as I
DavidSpickett wrote:
Going by the page (didn't see a link to a manual, maybe I missed it), MVE and
FPU are optional.
"Optional Helium technology (M-profile Vector Extension) supporting up to:"
"Optional FPU with support for half precision (fp16), single precision (fp32)
and double precision (f
@@ -340,8 +340,13 @@ Value *VPInstruction::generateInstruction(VPTransformState
&State,
auto *Phi = State.get(getOperand(0), 0);
// The loop step is equal to the vectorization factor (num of SIMD
// elements) times the unroll factor (num of SIMD instructions)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/2] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
https://github.com/JivanH created
https://github.com/llvm/llvm-project/pull/74824
This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds intrinsics of mop.r.[n] and mop.rr.[n] instructi
llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-llvm-ir
Author: Jivan Hakobyan (JivanH)
Changes
This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds intrinsics of
llvmbot wrote:
@llvm/pr-subscribers-llvm-support
Author: Jivan Hakobyan (JivanH)
Changes
This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds intrinsics of mop.r.[n] and mop.rr.
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/3] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
* Implemented :ref:`llvm.get.rounding `
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.
jthackray wrote:
Thanks,
https://github.com/karka228 updated
https://github.com/llvm/llvm-project/pull/74440
>From a80bf9d03f19d48c0aca4af7758dc49516da8825 Mon Sep 17 00:00:00 2001
From: Karl-Johan Karlsson
Date: Tue, 5 Dec 2023 10:03:00 +0100
Subject: [PATCH 1/5] [Sema] Implement support for -Wformat-signedness
In gc
JivanH wrote:
@topperc
@asb
@michaelmaitland
@wangpc-pp
https://github.com/llvm/llvm-project/pull/74824
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jthackray wrote:
> Going by the page (didn't see a link to a manual, maybe I missed it), MVE and
> FPU are optional.
>
> "Optional Helium technology (M-profile Vector Extension) supporting up to:"
> "Optional FPU with support for half precision (fp16), single precision (fp32)
> and double pre
@@ -899,6 +899,7 @@ Arm and AArch64 Support
* Arm Cortex-A520 (cortex-a520).
* Arm Cortex-A720 (cortex-a720).
* Arm Cortex-X4 (cortex-x4).
+ * Arm Cortex-M52 (cortex-m52).
davemgreen wrote:
Is it worth splitting this list into one for -target=aarch64 an
dtcxzyw wrote:
I guess you should split it into patch series.
+ [ ] MC support (and docs)
+ [ ] Sched support
+ [ ] ISel support
+ [ ] Builtin intrinsic support in clang
https://github.com/llvm/llvm-project/pull/74824
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@@ -20,3 +21,23 @@ int16x8_t incompat_neon_smc(int16x8_t splat)
__arm_streaming_compatible {
// expected-warning@+1 {{builtin call has undefined behaviour when called
from a streaming compatible function}}
return (int16x8_t)__builtin_neon_vqaddq_v((int8x16_t)splat,
(int8x
DavidSpickett wrote:
> Yes, that's correct. We enable all mandatory and optional architecture
> extensions, with the exception of crypto.
Cool.
That said then, should CDE be added?
```
Accelerator support
Optional coprocessor interface (64-bit) supporting up to 8 coprocessor units
for c
@@ -6,20 +6,21 @@
#include
__attribute__((target("sme")))
-void test_sme(svbool_t pg, void *ptr) {
+void test_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
svld1_hor_za8(0, 0, pg, ptr);
}
__attribute__((target("arch=armv8-a+sme")))
-void test_arch_sme(s
davemgreen wrote:
CDE is enabled per decode block and probably doesn't make a lot of sense to
enable universally. The cde options each pick between two features (CDE vs
co-processor), and so isn't quite the same as on vs off.
https://github.com/llvm/llvm-project/pull/74822
@@ -18,7 +18,7 @@
// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
// CHECK-CXX-NEXT:ret void
//
-void test_svzero_mask_za() {
+__arm_new_za void test_svzero_mask_za() {
SamTebbs33 wrote:
I did try `__arm_shared_za` but got
> '__arm_sha
@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
di
@@ -1375,6 +1381,12 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
"__nodebug__, __overloadable__))\n\n";
+ OS << "#ifdef __ARM_FEATURE_SME\n";
+ OS << "#define __asc __attribute__((arm
@@ -500,6 +506,12 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper
&Records) {
case GenArmSmeRangeChecks:
EmitSmeRangeChecks(Records, OS);
break;
+ case GenArmSmeStreamingAttrs:
SamTebbs33 wrote:
I remember you suggesting that we have the SM
https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/74594
>From 037dd51fd05ccd70f10dbf4ca75dd1f45e6548c4 Mon Sep 17 00:00:00 2001
From: Caroline Concatto
Date: Wed, 6 Dec 2023 14:02:23 +
Subject: [PATCH 1/3] [Clang][SVE2p1]Add svboolx2 and svboolx4 types fo
@@ -899,6 +899,7 @@ Arm and AArch64 Support
* Arm Cortex-A520 (cortex-a520).
* Arm Cortex-A720 (cortex-a720).
* Arm Cortex-X4 (cortex-x4).
+ * Arm Cortex-M52 (cortex-m52).
jthackray wrote:
Sure. Something like this?
```
+ --target=arm
+ * Arm Cort
https://github.com/fhahn closed https://github.com/llvm/llvm-project/pull/74762
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banach-space wrote:
> It seems like flang-new when being used as a linker with -shared included
> Fortran_main in the shared library. This seems wrong to me.
I am trying to recall the rationale behind that, but it's been a while :(
Here's a relevant discussion/bug that hasn't been resolved ye
Author: David Sherwood
Date: 2023-12-08T12:58:39Z
New Revision: c1cfa1757c208cd15efec3541aadea6bec52092d
URL:
https://github.com/llvm/llvm-project/commit/c1cfa1757c208cd15efec3541aadea6bec52092d
DIFF:
https://github.com/llvm/llvm-project/commit/c1cfa1757c208cd15efec3541aadea6bec52092d.diff
LOG
https://github.com/david-arm closed
https://github.com/llvm/llvm-project/pull/73326
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https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/73258
>From e0f245e8d6a395afac5de471b55358c7b730a170 Mon Sep 17 00:00:00 2001
From: Caroline Concatto
Date: Wed, 22 Nov 2023 10:03:50 +
Subject: [PATCH 1/7] [Clang][AArch64] Add fix vector types to header
@@ -0,0 +1,31 @@
+//=== AMDGPUAddrSpace.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/kmclaughlin-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/74594
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@@ -49,19 +48,33 @@
#include "clang/AST/OptionalDiagnostic.h"
#include "clang/AST/RecordLayout.h"
#include "clang/AST/StmtVisitor.h"
+#include "clang/AST/Type.h"
#include "clang/AST/TypeLoc.h"
#include "clang/Basic/Builtins.h"
-#include "clang/Basic/DiagnosticSema.h"
+#includ
tbaederr wrote:
I don't have the capacity to review this properly, but the changes to the
`static_assert` diagnostics should be split out IMO.
https://github.com/llvm/llvm-project/pull/74775
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http
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Mariusz Sikora (mariusz-sikora-at-amd)
Changes
---
Patch is 112.63 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/74836.diff
27 Files Affected:
- (modified) clang/include/clang/Basic/Builti
Author: Timm Baeder
Date: 2023-12-08T14:46:25+01:00
New Revision: d5e2cbd01a17edeb56aad2f161c76ce3f854676f
URL:
https://github.com/llvm/llvm-project/commit/d5e2cbd01a17edeb56aad2f161c76ce3f854676f
DIFF:
https://github.com/llvm/llvm-project/commit/d5e2cbd01a17edeb56aad2f161c76ce3f854676f.diff
L
https://github.com/tbaederr closed
https://github.com/llvm/llvm-project/pull/69713
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https://github.com/dtemirbulatov updated
https://github.com/llvm/llvm-project/pull/72827
>From 7aa69c9cb936b3883de7922f72ed9417be5a16f5 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov
Date: Mon, 20 Nov 2023 07:04:18 +
Subject: [PATCH 1/4] [AArch64][SME2] Add PEXT, PSEL builtins for SME2
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/4] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/72827
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@@ -1,13 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/72827
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@@ -896,9 +896,13 @@ Arm and AArch64 Support
Support has been added for the following processors (-mcpu identifiers in
parenthesis):
- * Arm Cortex-A520 (cortex-a520).
- * Arm Cortex-A720 (cortex-a720).
- * Arm Cortex-X4 (cortex-x4).
+ --target=arm
+ * Arm Cortex-M
@@ -896,9 +896,13 @@ Arm and AArch64 Support
Support has been added for the following processors (-mcpu identifiers in
parenthesis):
- * Arm Cortex-A520 (cortex-a520).
- * Arm Cortex-A720 (cortex-a720).
- * Arm Cortex-X4 (cortex-x4).
+ --target=arm
+ * Arm Cortex-M
@@ -896,9 +896,13 @@ Arm and AArch64 Support
Support has been added for the following processors (-mcpu identifiers in
parenthesis):
- * Arm Cortex-A520 (cortex-a520).
- * Arm Cortex-A720 (cortex-a720).
- * Arm Cortex-X4 (cortex-x4).
+ --target=arm
+ * Arm Cortex-M
@@ -331,3 +331,17 @@ namespace bitreverse {
char bitreverse3[__builtin_bitreverse32(0x12345678) == 0x1E6A2C48 ? 1 : -1];
char bitreverse4[__builtin_bitreverse64(0x0123456789ABCDEFULL) ==
0xF7B3D591E6A2C480 ? 1 : -1];
}
+
+namespace rotateleft {
+ char rotateleft1[__builti
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@@ -896,9 +896,13 @@ Arm and AArch64 Support
Support has been added for the following processors (-mcpu identifiers in
parenthesis):
- * Arm Cortex-A520 (cortex-a520).
- * Arm Cortex-A720 (cortex-a720).
- * Arm Cortex-X4 (cortex-x4).
+ --target=arm
+ * Arm Cortex-M
Author: erichkeane
Date: 2023-12-08T06:14:21-08:00
New Revision: 9b154dad5b465bfc45b962488682ed4f95e049a3
URL:
https://github.com/llvm/llvm-project/commit/9b154dad5b465bfc45b962488682ed4f95e049a3
DIFF:
https://github.com/llvm/llvm-project/commit/9b154dad5b465bfc45b962488682ed4f95e049a3.diff
LO
@@ -56,10 +56,10 @@ namespace Foo = A::B; // namespace alias
using Foo::myfunc; // using declaration
-using namespace Foo;// using directive
+//removing namespace foo; for quality naming
felipepiovezan wrote:
Hi @jeevanghimire, please note that t
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/5] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
@@ -896,9 +896,13 @@ Arm and AArch64 Support
Support has been added for the following processors (-mcpu identifiers in
parenthesis):
- * Arm Cortex-A520 (cortex-a520).
- * Arm Cortex-A720 (cortex-a720).
- * Arm Cortex-X4 (cortex-x4).
+ --target=arm
+ * Arm Cortex-M
@@ -34,7 +34,7 @@ namespace A {
int myfunc (int a);
int myfunc2(int a)
{
- return a + 2;
+return a + 2; //just changing tab not much
felipepiovezan wrote:
In general, we don't add diffs that are unrelated to
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