[PATCH] D109210: [clang-tidy] Attach fixit to warning, not note, in add_new_check.py example

mattbeardsley added a comment. Ah, and to your direct question: > BTW, the test wasn't checking for the note's message at all?" Right, the generated test file does not ever do `// CHECK-MESSAGES: :Row:Col: note: insert 'awesome'` (nor does the LIT setup here enforce that notes need to be check

[clang] 775ab78 - Support linking against OpenMP runtime on OpenBSD.

Author: Brad Smith Date: 2021-09-03T19:33:09-04:00 New Revision: 775ab780fd2a23cfc80ace571938ddd21d080173 URL: https://github.com/llvm/llvm-project/commit/775ab780fd2a23cfc80ace571938ddd21d080173 DIFF: https://github.com/llvm/llvm-project/commit/775ab780fd2a23cfc80ace571938ddd21d080173.diff LO

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370683. apivovarov retitled this revision from "[RISCV] Add SiFive core E20" to "[RISCV] Add SiFive cores E and S series". apivovarov edited the summary of this revision. apivovarov added a comment. Added SiFive cores E20, E21, E24, E34, S21, S54 and S76

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24 +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) -

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24 +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) -

[clang] d8cd780 - [clang] OpenBSD does not support C11 atomics or threads.

Author: Brad Smith Date: 2021-09-03T21:13:55-04:00 New Revision: d8cd7806310c51af912a647a6ca46de62ff13214 URL: https://github.com/llvm/llvm-project/commit/d8cd7806310c51af912a647a6ca46de62ff13214 DIFF: https://github.com/llvm/llvm-project/commit/d8cd7806310c51af912a647a6ca46de62ff13214.diff LO

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370687. apivovarov added a comment. fix typos Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-cpus.c

[clang] bce178a - Fix for commit d8cd7806310c51af912a647a6ca46de62ff13214.

Author: Brad Smith Date: 2021-09-03T21:20:37-04:00 New Revision: bce178a5ecf10df762cbda59c7f60cca8e52ce3a URL: https://github.com/llvm/llvm-project/commit/bce178a5ecf10df762cbda59c7f60cca8e52ce3a DIFF: https://github.com/llvm/llvm-project/commit/bce178a5ecf10df762cbda59c7f60cca8e52ce3a.diff LO

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov marked 4 inline comments as done. apivovarov added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:279 + +def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit, + FeatureStdExtM, craig

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: clang/test/Misc/target-invalid-cpu-note.c:195 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76 +// RISCV32: note: va

[PATCH] D109265: [X86][mingw] Modify the alignment of __m128/__m256/__m512 vector type for mingw

pengfei created this revision. pengfei added reviewers: rnk, mstorsjo, LiuChen3, LuoYuanke. pengfei requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. This is a follow up patch after D78564 and D108887

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370691. apivovarov marked an inline comment as done. apivovarov added a comment. main branch is unstable. pulling the hot fixes again CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 Files: clang/d

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370692. apivovarov added a comment. fix double space issue. Fri... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 Files: clang/docs/ReleaseNotes.rst clang/tes

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