jmolloy resigned from this revision.
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jmolloy added a comment.
I'm not the right person to review this.
http://reviews.llvm.org/D16586
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rmaprath added inline comments.
Comment at: test/CodeGen/aapcs-bitfield.c:312-317
@@ +311,8 @@
+
+ // BE: %[[PTR3:.*]] = bitcast %struct.st5a* %[[PTR2]] to i32*
+ // BE-NEXT: %[[LD:.*]] = load volatile i32, i32* %[[PTR3]], align 4
+ // BE-NEXT: %[[CLR:.*]] = and i32 %[[LD]], -1
rsmith added a subscriber: rsmith.
Comment at: test/CodeGen/aapcs-bitfield.c:312-317
@@ +311,8 @@
+
+ // BE: %[[PTR3:.*]] = bitcast %struct.st5a* %[[PTR2]] to i32*
+ // BE-NEXT: %[[LD:.*]] = load volatile i32, i32* %[[PTR3]], align 4
+ // BE-NEXT: %[[CLR:.*]] = and i32 %[[LD]],
rmaprath added a comment.
Ping?
http://reviews.llvm.org/D16586
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rmaprath marked 2 inline comments as done.
rmaprath added a comment.
http://reviews.llvm.org/D16586
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rmaprath updated this revision to Diff 46264.
rmaprath added a comment.
Addressing review comments by @rjmccall:
Moved all the AAPCS specific tweaks to EmitLValueForField(), this simplified
the patch a lot (now there is no mucking about a de-constructed GEP at
load/store points). In order to do
rmaprath added inline comments.
Comment at: lib/CodeGen/CGExpr.cpp:1761
@@ +1760,3 @@
+Ptr = Address(AdjustAAPCSBitfieldAccess(Dst, Info, false),
+ getContext().getTypeAlignInChars(Dst.getType()));
+
rjmccall wrote:
> This alignment computatio
rjmccall added a comment.
Well, that's certainly an interesting ABI rule.
A few high-level notes:
1. AAPCS requires the bit-field to be loaded on a store, even if the store
fills the entire container; that doesn't seem to be implemented in your patch.
2. Especially because of #1, let's not do
