@@ -24,6 +24,19 @@ def CSR_ILP32D_LP64D
: CalleeSavedRegs<(add CSR_ILP32_LP64,
F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
+defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),
+ V2M2, V4M2, V6M2, V24M2, V26M2, V28M
@@ -563,6 +615,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// directives.
for (const auto &Entry : CSI) {
int FrameIdx = Entry.getFrameIdx();
+if (FrameIdx >=0 &&
topperc wrote:
space between `>=` and `0`
https://github.com/ll
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
topperc wrote:
Does this test really require `riscv-registered-target`? It doesn't include any
headers and doesn't run any IR passes
https://github.com/llvm/llvm-project/pull/77560
_
@@ -24,6 +24,19 @@ def CSR_ILP32D_LP64D
: CalleeSavedRegs<(add CSR_ILP32_LP64,
F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
+defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),
+ V2M2, V4M2, V6M2, V24M2, V26M2, V28M
@@ -5400,6 +5400,16 @@ for clang builtin functions.
}];
}
+def RISCVVectorCCDocs : Documentation {
+ let Category = DocCatCallingConvs;
+ let Content = [{
+The ``riscv_vector_cc`` attribute can be applied to a function. It preserves 15
+registers namely, v1-v7 and v24-v31 as
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 7388b7422f9307dd5ae3fe3876a676d83d702daf
3e000d49ecc3769efa2051332c04163b84b0f9ae --
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Brandon Wu (4vtomat)
Changes
[RISCV] RISCV vector calling convention (1/2)
This is the vector calling convention based on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc,
the idea is to split between "scalar"
