[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/asb approved this pull request. LGTM. Thanks for your persistence on this! https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-co

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) wangpc-pp wrote: Though it's nearly impossible to have s

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) wangpc-pp wrote: The psABI says: > If used with an ISA t

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -50,11 +50,14 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) { void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign) { - if (STI.hasFeature(RISCV::FeatureRVE)) -repor

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) nemanjai wrote: What happens if we are using `ilp32e/lp6

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -38,3 +40,14 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D", 0

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

nemanjai wrote: > @nemanjai I'm curious if you have an interest / need to support RVE or not? I most certainly do. Thank you for alerting me to this PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llv

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

koute wrote: > Can you fire a PR for these changes? I think we should support it in > compiler-rt once we have merged this PR. Once this PR is merged, sure, I can make a PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

wangpc-pp wrote: > > As for your diffs, it seems that you only handle the > > `__riscv_save/restore_[2|1|0]`, which is incomplete. And the code is not > > different with non-rve cases? > > Yes, I mostly copy-pasted the existing code and removed all of the code > dealing with registers not ava

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

koute wrote: > But I think this patch can work just fine [...] Apart from vendors' need, the > request is mainly from Rust language community I think. To put our 3 cents here, [we](https://github.com/paritytech) also need it. We are (well, it's mostly me right now since it's still a prototype)

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -179,6 +180,11 @@ Assembly Support Supported Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which ca

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

asb wrote: @nemanjai I'm curious if you have an interest / need to support RVE or not? https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

wangpc-pp wrote: > @wangpc-pp did you have interested on helping psABI side? it would be great > if you can help since I suspect I don't have enough bandwidth to deal with > that soon. Yes, I'm glad to. I think what we need to do is to fix some Zdinx issues? :-) And, I think I have to explain

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

kito-cheng wrote: @wangpc-pp did you have interested on helping psABI side? it would be great if you can help since I suspect I don't have enough bandwidth to deal with that soon. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailin

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

kito-cheng wrote: Hmmm, RISC-V ISA is growth after https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257 again, I mean...we have zfinx and zdinx, which is also valid combination with rv32e/rv64e, so we may need to revise ilp32e ABI again on the psABI side, but my intention is not to b

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

asb wrote: The conclusion from the previous review was this was OK to merge. I think I held it up by not responding to a ping (apologies). I've had another scan through and don't see a problem with merging this and considering it experimental once Craig's review comments are addressed. For th

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -68,6 +68,11 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, TargetABI = ABI_Unknown; } + if ((TargetABI == RISCVABI::ABI::ABI_ILP32E || + (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && + FeatureBits[RISCV::FeatureStdExtD])

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -17134,30 +17133,64 @@ static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4}; static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}; -ArrayRef RISCV::getArgGPRs() { - static const MCPhysR

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -499,7 +514,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { // Calculate the size of the frame managed by the libcall. The libcalls are // implemented such that the stack will a

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -0,0 +1,221 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I-LP64E-FPELIM %s +; RUN: llc -mtriple=riscv64 -target-abi lp64e -ve

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

topperc wrote: What was the last bit of discussion on the phabricator review? I can no longer access it. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/lis

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Wang Pengcheng (wangpc-pp) Changes This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register co