[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/75760 >From 22fd20164e9d061a451555c5158f0a8ecb73f77e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 17 Dec 2023 18:18:43 -0800 Subject: [PATCH 1/3] [RISCV] Add sifive-p450 CPU. This is an out of order core wit

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

@@ -222,6 +222,11 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-pref

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

@@ -222,6 +222,11 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-p450 | FileCheck -check-pref

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/75760 >From 22fd20164e9d061a451555c5158f0a8ecb73f77e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 17 Dec 2023 18:18:43 -0800 Subject: [PATCH 1/2] [RISCV] Add sifive-p450 CPU. This is an out of order core wit

[llvm] [clang] [RISCV] Add sifive-p450 CPU. (PR #75760)

wangpc-pp wrote: Add test in `clang/test/Driver/riscv-cpus.c`? https://github.com/llvm/llvm-project/pull/75760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits