[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s | FileCheck %s --check-prefix=RV64 +; RUN: opt --passes=loop-vectorize --mtriple=aa

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s | FileCheck %s --check-prefix=RV64 +; RUN: opt --passes=loop-vectorize --mtriple=aa

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

wzssyqa wrote: Reverted https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 wangpc-pp wrote: Precommit this test. https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commit

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 wzssyqa wrote: https://github.com/llvm/llvm-project/pull/133690 https://github.com/llvm/llvm-project/pull/131781

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s | FileCheck %s --check-prefix=RV64 +; RUN: opt --passes=loop-vectorize --mtriple=aa

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s | FileCheck %s --check-prefix=RV64 +; RUN: opt --passes=loop-vectorize --mtriple=aa

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

https://github.com/arsenm commented: You can probably write a smaller test using SLPVectorizer, e.g. /llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commits mailing list cfe-commits@lists.l

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s | FileCheck %s --check-prefix=RV64 +; RUN: opt --passes=loop-vectorize --mtriple=aa

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 wzssyqa wrote: Do you mean that we should add this test case first and then this patch with update of the test case? https://github.com/llvm/llv

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -962,6 +962,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, static const unsigned ZvfhminZvfbfminPromoteOps[] = { ISD::FMINNUM, ISD::FMAXNUM, +ISD::FMINIMUMNUM, wangpc-pp wrote: RISCV changes should be in

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,407 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 arsenm wrote: You don't have a backend vectorization test. This PR contains no clang changes. You should delete the clang test and replace it

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

https://github.com/wangpc-pp commented: I think you should provide LLVM IR tests in `llvm/test/Transforms/LoopVectorize/**` instead of Clang tests. https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

wzssyqa wrote: ping https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,407 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 wzssyqa wrote: We have the backend test already. This PR fixes the front to generate vectorized IR from C code. https://github.com/llvm/llvm-p

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,407 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 arsenm wrote: Should not be testing the vectorizer in clang. This needs a pure IR test in the backend https://github.com/llvm/llvm-project/p

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

llvmbot wrote: @llvm/pr-subscribers-clang Author: YunQiang Su (wzssyqa) Changes Support auto-vectorize for fminimum_num and fmaximum_num. For ARM64 with SVE, scalable vector cannot support yet, and For RISCV Vector, scalable vector works well now. --- Patch is 33.38 KiB, truncated to 20

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

https://github.com/wzssyqa created https://github.com/llvm/llvm-project/pull/131781 Support auto-vectorize for fminimum_num and fmaximum_num. For ARM64 with SVE, scalable vector cannot support yet, and For RISCV Vector, scalable vector works well now. >From e367aaa410dcbb6f3d1c5803eac49dde6dae