farzonl wrote:
@RKSimon @topperc When you have time could I get a review. Thank you!
https://github.com/llvm/llvm-project/pull/90503
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@@ -654,6 +655,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine
&TM,
setOperationAction(ISD::FSIN , VT, Expand);
setOperationAction(ISD::FCOS , VT, Expand);
setOperationAction(ISD::FSINCOS, VT, Expand);
+ setOperationAction(ISD::FTAN,
@@ -674,6 +674,9 @@
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_FTAN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
f
@@ -654,6 +655,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine
&TM,
setOperationAction(ISD::FSIN , VT, Expand);
setOperationAction(ISD::FCOS , VT, Expand);
setOperationAction(ISD::FSINCOS, VT, Expand);
+ setOperationAction(ISD::FTAN,
@@ -674,6 +674,9 @@
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_FTAN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
f
@@ -674,6 +674,9 @@
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_FTAN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
t
tschuett wrote:
Firstly, it is a nit. The IRTranslator translates LLVM-IR into GMIR for
GlobalIsel. Testing the IRTranslator is independent of any SDAG changes.
https://github.com/llvm/llvm-project/pull/90503
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farzonl wrote:
> Nit: the `declare` is not necessary anymore. You touched the IRTranslator
> without a test at, e.g.,
> https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The aarch64 backend tag is a misnomer because adding `G_FTAN` caused
tschuett wrote:
Nit: the `declare` is not necessary anymore. You touched the IRTranslator
without a test at, e.g.,
https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
https://github.com/llvm/llvm-project/pull/90503
_
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-llvm-analysis
Author: Farzon Lotfi (farzonl)
Changes
This change is an implementation of #87367's investigation on
supporting IEEE math operations as intrinsics.
Which was discussed in this RFC:
https://discourse.llv
https://github.com/farzonl ready_for_review
https://github.com/llvm/llvm-project/pull/90503
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/90503
This change is an implementation of #87367's investigation on supporting IEEE
math operations as intrinsics.
Which was discussed in this RFC:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
If you
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