https://github.com/Keenuts closed
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Keenuts wrote:
Merging to unblock the structurizer work.
Let me know if you had a specific SEMA check in mind to add in the end!
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/103299
From 04886f07618a283cc56d8a28aaf99e16d3897855 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Tue, 13 Aug 2024 14:39:03 +0200
Subject: [PATCH] [clang][HLSL] Add WaveIsLaneFirst() intrinsic
M
farzonl wrote:
> > We have this work tracked here: #99158
> > there should be some dxil specific tasks.
>
> Seems like most boxes would be checked by this PR, except Sema checks:
>
> * what kind of Sema checks would be required for this one?
> Also, the intrinsic name in the issue is using ca
@@ -18660,6 +18660,10 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
llvm::FunctionType::get(IntTy, {}, false),
"__hlsl_wave_get_lane_index",
{}, false, true));
}
+ case Builtin::BI__builtin_hlsl_wave_is_first_lane: {
+Intrinsic::ID ID = CGM.getH
farzonl wrote:
closes #99158
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/michalpaszkowski approved this pull request.
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -18660,6 +18660,10 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
llvm::FunctionType::get(IntTy, {}, false),
"__hlsl_wave_get_lane_index",
{}, false, true));
}
+ case Builtin::BI__builtin_hlsl_wave_is_first_lane: {
+Intrinsic::ID ID = CGM.getH
https://github.com/farzonl approved this pull request.
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -18660,6 +18660,10 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
llvm::FunctionType::get(IntTy, {}, false),
"__hlsl_wave_get_lane_index",
{}, false, true));
}
+ case Builtin::BI__builtin_hlsl_wave_is_first_lane: {
+Intrinsic::ID ID = CGM.getH
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Keenuts wrote:
> This commits add the WaveIsFirstLane() hlsl intrinsinc. This intrinsic uses
> the convergence intrinsincs for the SPIR-V backend. On the DXIL side, I'm not
> sure what the strategy is so this is implemented like in DXC: a simple
> builtin function. (DXC didn't used convergence
Keenuts wrote:
> > We have this work tracked here: #99158
> > there should be some dxil specific tasks.
>
> Seems like most boxes would be checked by this PR, except Sema checks:
>
> * what kind of Sema checks would be required for this one?
> Also, the intrinsic name in the issue is using ca
Keenuts wrote:
> We have this work tracked here: #99158
>
> there should be some dxil specific tasks.
Seems like most boxes are checked, except Sema checks:
- what kind of Sema checks would be required for this one?
Also, the intrinsic name in the issue is using camel case vs snake case for
t
farzonl wrote:
We have this work tracked here:
https://github.com/llvm/llvm-project/issues/99158
there should be some dxil specific tasks.
https://github.com/llvm/llvm-project/pull/103299
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https:
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
@llvm/pr-subscribers-backend-x86
Author: Nathan Gauër (Keenuts)
Changes
This commits add the WaveIsFirstLane() hlsl intrinsinc. This intrinsic uses the
convergence intrinsincs for the SPIR-V backend. On the DXIL side, I'm not sure
what th
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/103299
This commits add the WaveIsFirstLane() hlsl intrinsinc. This intrinsic uses the
convergence intrinsincs for the SPIR-V backend. On the DXIL side, I'm not sure
what the strategy is. (DXC didn't used convergence
17 matches
Mail list logo
