[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120 >From aaee7cfdea325459d68bc4e7205d7e25ca045d1a Mon Sep 17 00:00:00 2001 From: Piyou Chen Date: Sun, 14 Jan 2024 19:41:59 -0800 Subject: [PATCH 1/9] [RISCV] Relax march string order constraint --- clang/test/Driver/

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } +static Error splitExtsByUnderscore(StringRef Exts, + std::vector &SplitExts) { + SmallVector Split; + if (Exts.empty()) +retu

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } +static Error splitExtsByUnderscore(StringRef Exts, + std::vector &SplitExts) { + SmallVector Split; + if (Exts.empty()) +retu

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -715,6 +815,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, unsigned XLen = HasRV64 ? 64 : 32; std::unique_ptr ISAInfo(new RISCVISAInfo(XLen)); + SmallVector SeenExts; BeMg wrote: Use MapVector instead of SmallVec

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } +static Error splitExtsByUnderscore(StringRef Exts, + std::vector &SplitedExts) { BeMg wrote: Done https://github

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120 >From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001 From: Piyou Chen Date: Sun, 14 Jan 2024 19:41:59 -0800 Subject: [PATCH 1/6] [RISCV] Relax march string order constraint --- clang/test/Driver/

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -715,6 +815,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, unsigned XLen = HasRV64 ? 64 : 32; std::unique_ptr ISAInfo(new RISCVISAInfo(XLen)); + SmallVector SeenExts; topperc wrote: Maybe SeenExts should be a Set

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -337,10 +319,79 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { } } +TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) { + for (StringRef Input : + {"rv32imfad", "rv32im_fa_d", "rv32im2p0fad", "rv32i2p1m2p0fad"}) { +auto MaybeISAInfo =

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -156,9 +156,8 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s // RV32L: error: invalid arch name 'rv32l' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s -// RV32I

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -785,153 +878,61 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, Minor = Version->Minor; } -ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor}); +// Postpone AddExtension until end of this function +SeenEx

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -337,10 +319,79 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { } } +TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) { + for (StringRef Input : + {"rv32imfad", "rv32im_fa_d", "rv32im2p0fad", "rv32i2p1m2p0fad"}) { +auto MaybeISAInfo =

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

MaskRay wrote: > Address the > https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 > > This patch relax the -march string for accept any order. Perhaps: Follow https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 by dropping the order requirement of `-march`.

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

https://github.com/MaskRay approved this pull request. GCC patch has just landed: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643411.html https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -156,9 +156,8 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s // RV32L: error: invalid arch name 'rv32l' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s -// RV32I

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

asb wrote: Just to check, can someone confirm if gcc is now handling ISA strings in this way too? I do think this is the right direction to go but haven't done a detailed code review of this approach yet. https://github.com/llvm/llvm-project/pull/78120 _