[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-13 Thread Jim Lin via cfe-commits
https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/111653 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Craig Topper via cfe-commits
@@ -102,7 +102,7 @@ bool RISCVTargetInfo::validateAsmConstraint( return true; case 'v': // A vector register. -if (Name[1] == 'r' || Name[1] == 'm') { +if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') { topperc wrote: Nevermind. I gues

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Craig Topper via cfe-commits
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/111653 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Craig Topper via cfe-commits
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/111653 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Craig Topper via cfe-commits
@@ -29,6 +29,14 @@ vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) { return ret; } +vint32m1_t test_vd(vint32m1_t a, vint32m1_t b) { +// CHECK-LABEL: define{{.*}} @test_vd +// CHECK: %0 = tail call asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vd,^vd"( %a, %b) + vint32m1_t

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Sam Elliott via cfe-commits
@@ -29,6 +29,14 @@ vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) { return ret; } +vint32m1_t test_vd(vint32m1_t a, vint32m1_t b) { +// CHECK-LABEL: define{{.*}} @test_vd +// CHECK: %0 = tail call asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vd,^vd"( %a, %b) + vint32m1_t

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Craig Topper via cfe-commits
@@ -102,7 +102,7 @@ bool RISCVTargetInfo::validateAsmConstraint( return true; case 'v': // A vector register. -if (Name[1] == 'r' || Name[1] == 'm') { +if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') { topperc wrote: This needs to be

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Craig Topper via cfe-commits
https://github.com/topperc requested changes to this pull request. https://github.com/llvm/llvm-project/pull/111653 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-11 Thread Sam Elliott via cfe-commits
https://github.com/lenary approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/111653 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

2024-10-10 Thread Jim Lin via cfe-commits
https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/111653 >From 80768f580d4ef6b9841b22ee5b287a87d9f25951 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 9 Oct 2024 11:37:46 +0800 Subject: [PATCH 1/2] [RISCV] Add support for inline asm constraint vd It constrains ve