[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-16 Thread Anton Sidorenko via cfe-commits
https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/108406 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-13 Thread Yingwei Zheng via cfe-commits
https://github.com/dtcxzyw approved this pull request. LG https://github.com/llvm/llvm-project/pull/108406 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-13 Thread Anton Sidorenko via cfe-commits
https://github.com/asi-sc updated https://github.com/llvm/llvm-project/pull/108406 >From 0c2925d18e8e4312a16d081c1c97d3298b85e8d4 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Mon, 2 Sep 2024 13:25:39 +0300 Subject: [PATCH 1/2] [RISCV] Add Syntacore SCR7 processor definition Syntacore S

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-13 Thread Anton Sidorenko via cfe-commits
@@ -502,3 +502,28 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=synt

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-12 Thread Yingwei Zheng via cfe-commits
@@ -502,3 +502,28 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=synt

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-12 Thread via cfe-commits
llvmbot wrote: @llvm/pr-subscribers-clang Author: Anton Sidorenko (asi-sc) Changes Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core. The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march. Overview: https://syntacore.com/products/scr7 Scheduling model will be added in

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-12 Thread via cfe-commits
llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Anton Sidorenko (asi-sc) Changes Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core. The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march. Overview: https://syntacore.com/products/scr7 Scheduling model will be

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

2024-09-12 Thread Anton Sidorenko via cfe-commits
https://github.com/asi-sc created https://github.com/llvm/llvm-project/pull/108406 Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core. The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march. Overview: https://syntacore.com/products/scr7 Scheduling model will be added in a subs