github-actions[bot] wrote:
@dong-miao Congratulations on having your first Pull Request (PR) merged into
the LLVM Project!
Your changes will be combined with recent changes from other authors, then
tested by our [build bots](https://lab.llvm.org/buildbot/). If there is a
problem with a buil
Xinlong-Wu wrote:
@dong-miao don‘t have write access, I help him to merge
https://github.com/llvm/llvm-project/pull/111668
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https://github.com/Xinlong-Wu closed
https://github.com/llvm/llvm-project/pull/111668
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https://github.com/lenary approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/111668
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https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/25] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/24] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/23] Update RISCVSyst
@@ -129,6 +129,7 @@ on support follow.
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smepmp``Supported
+ ``Smrnmi``Supported
dong-miao wrote:
Okay, thanks for your help.
https://github.com/llvm/llvm-project/pull/
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/23] Update RISCVSyst
@@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00010;
}
+
+def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
lenary wrote:
Nice, thanks!
https://github.com/llvm/llvm-project/pull/111668
__
@@ -129,6 +129,7 @@ on support follow.
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smepmp``Supported
+ ``Smrnmi``Supported
lenary wrote:
This should probably be "Assembly Support" - some of the other `*ret`
ins
@@ -931,6 +931,10 @@ def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0,
"'Smepmp' (Enhanced Physical Memory Protection)">;
+def FeatureStdExtSmrnmi
+: RISCVExtension<"smrnmi", 1, 0,
+ "'Smrnmi' (Extension for Resumable Non
@@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
+def riscv_mnret
@@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
csrrs t2, 0xB1F, zero
+##
+# Machine Counter Setup
dong-miao wrote:
Okay, I haven't made any modifications to the content of this file
https://github.com/llvm/llvm-proj
@@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00010;
}
+
+def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
dong-miao wrote:
Thanks for your help. I have added the relevant content.
https://github.com/llvm/l
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/22] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/21] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/20] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/19] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/18] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/17] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/16] Update RISCVSyst
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/111668
>From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001
From: dong-miao <65881865+dong-m...@users.noreply.github.com>
Date: Wed, 9 Oct 2024 18:49:38 +0800
Subject: [PATCH 01/15] Update RISCVSyst
@@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
+def riscv_mnret
@@ -931,6 +931,10 @@ def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0,
"'Smepmp' (Enhanced Physical Memory Protection)">;
+def FeatureStdExtSmrnmi
+: RISCVExtension<"smrnmi", 1, 0,
+ "'Smrnmi' (Extension for Resumable Non
@@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00010;
}
+
+def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
lenary wrote:
Does this need a `Requires=[HasStdExtSmrnmi]` (And a definition of
`HasStdExtSmrnmi`)
@@ -276,6 +276,14 @@ foreach i = 0...15 in {
foreach i = 0...63 in
def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
+//===--===//
+// Machine Non-Maskable Interrupt Handling
+//===-
@@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
csrrs t2, 0xB1F, zero
+##
+# Machine Counter Setup
topperc wrote:
Section title is incorrect.
The registers are already tested in rv32-machine-csr-names.s but they shou
@@ -276,6 +276,14 @@ foreach i = 0...15 in {
foreach i = 0...63 in
def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
+//===--===//
+// Machine Non-Maskable Interrupt Handling
+//===-
https://github.com/topperc edited
https://github.com/llvm/llvm-project/pull/111668
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