mgoudar wrote:
> Lets wait another day or two, since someone may have additional comments.
> Thanks @mgoudar!
sure. thank you.
https://github.com/llvm/llvm-project/pull/130587
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mgoudar wrote:
thank you.
https://github.com/llvm/llvm-project/pull/130587
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@@ -121,6 +121,30 @@
// MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN: | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/130587
>From 4f9c5b5b844a61b760a3462994c7736542c14ca4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH 1/5] [MIPS] Add MIPS i6400 and i6500 processors
The i6400 a
@@ -121,6 +121,30 @@
// MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN: | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i
djtodoro wrote:
Lets wait another day or two, since someone may have additional comments.
Thanks @mgoudar!
https://github.com/llvm/llvm-project/pull/130587
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https://github.com/djtodoro approved this pull request.
https://github.com/llvm/llvm-project/pull/130587
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@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};
- enum class CPU { P5600 };
+ enum class CPU { P5600, I6400 };
mgoudar wrote:
Thanks for quick review!
yes. i6
@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
"MipsSubtarget::CPU::P5600",
"The P5600 Processor", [FeatureMips32r5]>;
+// I6500 is multicluster version of I6400. Both are based on s
@@ -47,14 +47,16 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
.Case("mips64r6", true)
.Case("octeon", true)
.Case("octeon+", true)
+ .Case("i6400", true)
+ .Case("i6500", true)
.Default(false);
}
static constexpr llvm::StringLi
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/130587
>From 4f9c5b5b844a61b760a3462994c7736542c14ca4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH 1/4] [MIPS] Add MIPS i6400 and i6500 processors
The i6400 a
@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
"MipsSubtarget::CPU::P5600",
"The P5600 Processor", [FeatureMips32r5]>;
+// I6500 is multicluster version of I6400. Both are based on s
@@ -101,6 +101,8 @@ Changes to the LoongArch Backend
Changes to the MIPS Backend
---
+* `-mcpu=i6400` and `-mcpu=i6500` was added.
brad0 wrote:
Were instead of was.
https://github.com/llvm/llvm-project/pull/130587
https://github.com/mgoudar created
https://github.com/llvm/llvm-project/pull/130587
The i6400 and i6500 are high performance multi-core microprocessors from MIPS
that provide best in class power efficiency for use in system-on-chip (SoC)
applications. i6400 and i6500 implements Release 6 of t
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/130587
>From 4f9c5b5b844a61b760a3462994c7736542c14ca4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH 1/2] [MIPS] Add MIPS i6400 and i6500 processors
The i6400 a
https://github.com/djtodoro requested changes to this pull request.
Thanks for working on this.
https://github.com/llvm/llvm-project/pull/130587
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@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};
- enum class CPU { P5600 };
+ enum class CPU { P5600, I6400 };
djtodoro wrote:
do we need "i6500" here as well
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};
- enum class CPU { P5600 };
+ enum class CPU { P5600, I6400 };
djtodoro wrote:
So, we do not use this in this
https://github.com/mgoudar edited
https://github.com/llvm/llvm-project/pull/130587
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llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Mallikarjuna Gouda (mgoudar)
Changes
The i6400 and i6500 are high performance multi-core microprocessors from MIPS
that provide best in class power efficiency for use in system-on-chip (SoC)
applications. i6400 and i6500 implement
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
CPUName == "mips64r5" || CPUName == "octeon" ||
CPUName == "octeon+",
"-march=mips64r2", Flags);
- addMultilibFlag(CPUName == "mips64r6",
https://github.com/djtodoro edited
https://github.com/llvm/llvm-project/pull/130587
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llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Mallikarjuna Gouda (mgoudar)
Changes
The i6400 and i6500 are high performance multi-core microprocessors from MIPS
that provide best in class power efficiency for use in system-on-chip (SoC)
applications. i6400 and i6500 implements Relea
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