@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
s-perron wrote:
https://github.com/llvm
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
s-perron wrote:
I don't think anything
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
s-perron wrote:
Sorry I missed this in
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `llvm-clang-x86_64-darwin`
running on `doug-worker-3` while building `clang,llvm` at step 6
"test-build-unified-tree-check-all".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/23/builds/3882
Here is
https://github.com/inbelic closed
https://github.com/llvm/llvm-project/pull/111010
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https://github.com/farzonl approved this pull request.
https://github.com/llvm/llvm-project/pull/111010
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@@ -0,0 +1,44 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend for various types an
https://github.com/llvm-beanz approved this pull request.
https://github.com/llvm/llvm-project/pull/111010
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bogner wrote:
It would probably be good to have some test coverage for int16, half, and
double here
https://github.com/llvm/llvm-project/pull/111010
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https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 01/14] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 01/14] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a
https://github.com/bogner approved this pull request.
Looks good once Chris's comments and the clang-format issue are resolved.
https://github.com/llvm/llvm-project/pull/111010
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github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff a4916d200518ac077be93995af18bd80fcb89cc2
49edfec7f8d2fb84144ef903bc5db3ab2099a1ae --e
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 01/11] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a
https://github.com/llvm-beanz edited
https://github.com/llvm/llvm-project/pull/111010
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@@ -1956,6 +1956,26 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
return true;
break;
}
+ case Builtin::BI__builtin_hlsl_wave_read_lane_at: {
+if (SemaRef.checkArgCount(TheCall, 2))
+ return true;
+
+// Ensure ind
https://github.com/llvm-beanz commented:
One small nit, but otherwise looks good.
https://github.com/llvm/llvm-project/pull/111010
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@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlaneat)
---
@@ -428,6 +431,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
case TargetOpcode::G_INTRINSIC:
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+ case TargetOpcode::G_INTRINSIC_CONVERGENT:
s-perron wrote:
The extra convergence information i
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 01/11] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 01/10] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
inbelic wrote:
Good catch. There are no ignored diagnostics and it
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
@@ -18835,6 +18835,24 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_l
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
llvm-beanz wrote:
I'm always suspicious when I see `verify-ignore-u
inbelic wrote:
I will go ahead and merge this tomorrow if there are no other comments.
https://github.com/llvm/llvm-project/pull/111010
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@@ -428,6 +431,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
case TargetOpcode::G_INTRINSIC:
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+ case TargetOpcode::G_INTRINSIC_CONVERGENT:
inbelic wrote:
Afaict, not within this section of t
https://github.com/farzonl approved this pull request.
LGTM
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@@ -428,6 +431,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
case TargetOpcode::G_INTRINSIC:
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+ case TargetOpcode::G_INTRINSIC_CONVERGENT:
farzonl wrote:
Is there anything that distinguishes
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/9] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a cl
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/8] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a cl
@@ -2015,6 +2015,13 @@ _HLSL_AVAILABILITY(shadermodel, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_is_first_lane)
__attribute__((convergent)) bool WaveIsFirstLane();
+// \brief Returns the value of the expression for the given lane index within
+// the specified wave.
+templa
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/111010
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@@ -2015,6 +2015,13 @@ _HLSL_AVAILABILITY(shadermodel, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_is_first_lane)
__attribute__((convergent)) bool WaveIsFirstLane();
+// \brief Returns the value of the expression for the given lane index within
+// the specified wave.
+templa
@@ -2015,6 +2015,13 @@ _HLSL_AVAILABILITY(shadermodel, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_is_first_lane)
__attribute__((convergent)) bool WaveIsFirstLane();
+// \brief Returns the value of the expression for the given lane index within
+// the specified wave.
+templa
@@ -18835,6 +18835,24 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_l
@@ -2015,6 +2015,13 @@ _HLSL_AVAILABILITY(shadermodel, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_is_first_lane)
__attribute__((convergent)) bool WaveIsFirstLane();
+// \brief Returns the value of the expression for the given lane index within
+// the specified wave.
+templa
@@ -1956,6 +1956,26 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
return true;
break;
}
+ case Builtin::BI__builtin_hlsl_wave_read_lane_at: {
+if (SemaRef.checkArgCount(TheCall, 2))
+ return true;
+
+// Ensure ind
@@ -18835,6 +18835,24 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_l
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/7] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a cl
@@ -18835,6 +18835,22 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_l
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/111010
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@@ -83,6 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/6] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a cl
@@ -82,5 +82,6 @@ let TargetPrefix = "spv" in {
[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
[IntrConvergent]>;
+ def int_spv_wave_rea
@@ -83,6 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -82,5 +82,6 @@ let TargetPrefix = "spv" in {
[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
[IntrConvergent]>;
+ def int_spv_wave_rea
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend
+
+; CHECK-DAG: %[[#uint
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend
+
+; CHECK-DAG: %[[#uint
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend
+
+; CHECK-DAG: %[[#uint
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend
+
+; CHECK-DAG: %[[#uint
@@ -0,0 +1,56 @@
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s |
FileCheck %s
+
+; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op
+
+define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK:
@@ -0,0 +1,56 @@
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s |
FileCheck %s
+
+; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op
+
+define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK:
@@ -0,0 +1,56 @@
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s |
FileCheck %s
+
+; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op
+
+define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK:
@@ -0,0 +1,56 @@
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s |
FileCheck %s
+
+; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op
+
+define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK:
@@ -2653,6 +2653,22 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
+ case Intrinsic::spv_wave_read_lane_at: {
+assert(I.getNumOperands() == 4);
@@ -83,6 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -fincl
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/111010
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@@ -18835,6 +18835,22 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_l
@@ -18835,6 +18835,22 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_l
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend
+
+; CHECK-DAG: %[[#uint
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/3] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a cl
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/3] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a cl
@@ -2653,6 +2653,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
+ case Intrinsic::spv_wave_read_lane_at: {
+assert(I.getNumOperands() == 4);
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/111010
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