https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/99042
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momchil-velikov wrote:
Rebased.
https://github.com/llvm/llvm-project/pull/99042
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@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mattr=+sve2 < %s | FileCheck %s
+; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define @famin_f
@@ -717,6 +717,11 @@ let Predicates = [HasSVEorSME] in {
defm FDIV_ZPZZ : sve_fp_bin_pred_hfd;
} // End HasSVEorSME
+let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
+ defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd;
+ defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd;
+}
+
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99042
>From aa74d04751558f3ab47d566c91fb8ad178df0dce Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 16 Jul 2024 13:37:34 +0100
Subject: [PATCH 1/3] [AArch64] Implement intrinsics for SVE FAMIN/FAMAX
@@ -717,6 +717,11 @@ let Predicates = [HasSVEorSME] in {
defm FDIV_ZPZZ : sve_fp_bin_pred_hfd;
} // End HasSVEorSME
+let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
+ defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd;
+ defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd;
+}
+
@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mattr=+sve2 < %s | FileCheck %s
+; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define @famin_f
https://github.com/paulwalker-arm approved this pull request.
A couple of suggestions but otherwise this looks good to me.
https://github.com/llvm/llvm-project/pull/99042
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https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/99042
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99042
>From aa74d04751558f3ab47d566c91fb8ad178df0dce Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 16 Jul 2024 13:37:34 +0100
Subject: [PATCH 1/2] [AArch64] Implement intrinsics for SVE FAMIN/FAMAX
@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
paulwalker-arm wrote:
Yep, the latter. We use it here because the ISD node exists for other reasons
and so was convenient to reuse here.
In ge
@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
momchil-velikov wrote:
How about:
```
case Intrinsic::aarch64_sve_fmin_u:
return DAG.getNode(AArch64ISD::FMIN_PRED, SDLoc(N), N->getValueT
@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
paulwalker-arm wrote:
Is it necessary to create dedicated AArch64ISD nodes? We normally reserve that
for cases where additional DAG combines ar
@@ -2385,3 +2385,8 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in
{
def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", "dd$$i", "f", MergeNone,
"aarch64_sve_bfmlslb_lane", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<3,
ImmCheck0_7>]>;
def SVBFMLSLT_LANE :
@@ -2385,3 +2385,8 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in
{
def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", "dd$$i", "f", MergeNone,
"aarch64_sve_bfmlslb_lane", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<3,
ImmCheck0_7>]>;
def SVBFMLSLT_LANE :
https://github.com/CarolineConcatto approved this pull request.
https://github.com/llvm/llvm-project/pull/99042
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