[clang] [RISCV] Recognize veyron-v1 processor in clang driver. (PR #66703)

https://github.com/mgudim closed https://github.com/llvm/llvm-project/pull/66703 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Recognize veyron-v1 processor in clang driver. (PR #66703)

https://github.com/michaelmaitland approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/66703 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Recognize veyron-v1 processor in clang driver. (PR #66703)

llvmbot wrote: @llvm/pr-subscribers-clang Changes Subsequent PRs will add the scheduling model and support for macro fusions. --- Full diff: https://github.com/llvm/llvm-project/pull/66703.diff 3 Files Affected: - (modified) clang/test/Driver/riscv-cpus.c (+25) - (modified) clang/test/

[clang] [RISCV] Recognize veyron-v1 processor in clang driver. (PR #66703)

https://github.com/mgudim created https://github.com/llvm/llvm-project/pull/66703 Subsequent PRs will add the scheduling model and support for macro fusions. >From 414ecd5d2abe13767668a89045be2ef2f460509d Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Mon, 18 Sep 2023 17:01:40 -0400 Subjec