https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/70294
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asb wrote:
> Xiangshan is of great famousness in China and there is already a community in
> which many individual developers and organiztions/companies like PLCT, T-Head
> have participated. So I think we needn't worry about the maintenance. :-)
Thanks for that extra context!
https://github.
wangpc-pp wrote:
Xiangshan is of great famousness in China and there is already a community in
which many individual developers and organiztions/companies like PLCT, T-Head
have participated. So I think we needn't worry about the maintenance. :-)
https://github.com/llvm/llvm-project/pull/70294
asb wrote:
> > @dtcxzyw Could you please confirm the status of this core - is it
> > commercially available, an academic test chip, something else?
>
> It's maintained by Beijing Institute of Open Source Chip (BOSC), a non-profit
> organziation founded by companies and researech institutions.
https://github.com/MaskRay edited
https://github.com/llvm/llvm-project/pull/70294
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@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
https://github.com/MaskRay approved this pull request.
https://github.com/llvm/llvm-project/pull/70294
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dtcxzyw wrote:
Any more questions about XiangShan? If there is no question, I will merge this
PR tomorrow.
https://github.com/llvm/llvm-project/pull/70294
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poemonsense wrote:
> Please update the official document then. :-)
I'll do it. We did not list it previously because it is not the usual thing for
user programs, as we were initially implementing it for internal usage. Sorry
for causing the confusion.
https://github.com/llvm/llvm-project/pull
poemonsense wrote:
> @dtcxzyw Could you please confirm the status of this core - is it
> commercially available, an academic test chip, something else?
It's maintained by Beijing Institute of Open Source Chip (BOSC), a non-profit
organziation founded by companies and researech institutions. It
poemonsense wrote:
> LGTM in general, except one question: will zicbom and zicboz be in the final
> RTL?
Yes, it's in the final RTL.
https://github.com/llvm/llvm-project/pull/70294
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asb wrote:
@dtcxzyw Could you please confirm the status of this core - is it commercially
available, an academic test chip, something else?
https://github.com/llvm/llvm-project/pull/70294
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https:/
wangpc-pp wrote:
> > LGTM in general, except one question: will zicbom and zicboz be in the
> > final RTL?
>
> You can find the full implementation of `zicbom` and `zicboz` here:
> [OpenXiangShan/XiangShan@ca18a0b](https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/70294
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@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
https://github.com/wangpc-pp approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/70294
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dtcxzyw wrote:
> LGTM in general, except one question: will zicbom and zicboz be in the final
> RTL?
You can find the full implementation of `zicbom` and `zicboz` here:
https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091cb90bf98f25.
cc @poemonsense
https://github.
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
Co-auth
wangpc-pp wrote:
LGTM in general, except one question: will zicbom and zicboz be in the final
RTL?
https://github.com/llvm/llvm-project/pull/70294
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llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Yingwei Zheng (dtcxzyw)
Changes
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/late
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/), N
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