[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added a comment. In D99158#2695125 , @craig.topper wrote: > Also can you please explain the vector codegen plan at a high level? Do you > intend to support auto vectorization or just using vector_size in C? Currently, it just supports vector type op

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 338414. Jim added a comment. Fix typo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/Builtins.de

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/Builtins.def:41 // E -> ext_vector, followed by the number of elements and the base type. +// e -> Register sized Vector, followd by the base type and +// its width is the same as the register size

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added a comment. Also can you please explain the vector codegen plan at a high level? Do you intend to support auto vectorization or just using vector_size in C? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll:25 + %1 = bitcast i32 %b.coerce to <4 x i8> + %2 = tail call <4 x i8> @llvm.riscv.add8.v4i8(<4 x i8> %0, <4 x i8> %1) + %3 = bitcast <4 x i8> %2 to i32 I'm still no

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:762 + for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) +setOperationAction(Opc, VT, Expand); + craig.topper wrote: > You probably need handling for insert_vect

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 338017. Jim added a comment. 1. Updating D99158 : [RISCV][WIP] Implement intrinsics for P extension # 2. Enter a brief description of the changes included in this update. 3. The first line is used as subject, next lines as comment

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17944 + + // P extension +#define EMIT_BUILTIN(NAME, INT) \ Please put this above the vector extension since the comment says "vector builtins are handled from here" =

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setOperationAction(ISD::BITCAST, VT, Legal); + Jim wrote: > craig.topper wrote: > > What about bitcast from float/double to any of these vector types? I'm > > guess t

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 335428. Jim added a comment. Subtarget.hasStdExtP() -> Subtarget.hasStdExtZpn() for addRegisterClass CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17944 + + // P extension +#define EMIT_BUILTIN(NAME, INT) \ I have concern here. It has lots of duplicate code if the code style is the same as B in the top. And the name of macro is not goo

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setOperationAction(ISD::BITCAST, VT, Legal); + craig.topper wrote: > What about bitcast from float/double to any of these vector types? I'm guess > that's not legal.

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 335416. Jim edited the summary of this revision. Jim added a comment. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/B

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added a comment. In D99158#2645796 , @craig.topper wrote: > What are we gaining from making the intrinsics use vector types if no vector > operations are supported other than the intrinsics? Why can't we just use an > xlen integer type? It can supp

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:715-732 +if (Subtarget.is64Bit()) { + addTypeForP(MVT::v8i8, MVT::i64); + addTypeForP(MVT::v4i16, MVT::i64); + addTypeForP(MVT::v2i32, MVT::i64); +} else { + add

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added a comment. What are we gaining from making the intrinsics use vector types if no vector operations are supported other than the intrinsics? Why can't we just use an xlen integer type? Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setO

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

jrtc27 added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11170-11175 // RISC-V V-extension def err_riscvv_builtin_requires_v : Error< "builtin requires 'V' extension support to be enabled">; +// RISC-V P-extension +def err_riscvv_builtin_re