[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG5821a58d8e4c: [RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'. (authored by HsiangKai). Repository: rG LLVM Github Monore

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98616/new/ https://reviews.llvm.org/D98616 _

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

HsiangKai updated this revision to Diff 333806. HsiangKai added a comment. Use 'vr' for vector registers and 'vm' for vector mask registers. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98616/new/ https://reviews.llvm.org/D98616 Files: clang/li

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

kito-cheng added a comment. Provide more implementation detail on GCC, - if a letter are used as a prefix of multi-char constraint, then it can't be used as a single letter constraint - e.g. If we defined `vr` and `vm` then we can't define `v` as constraint - constraint with same prefix should

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

jrtc27 added a comment. In D98616#2626094 , @jrtc27 wrote: > In D98616#2626093 , @kito-cheng > wrote: > >> GCC use `vr` for vector register and `vm` for vector mask register. > > How does that even work? Aren't mul

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

jrtc27 added a comment. In D98616#2626093 , @kito-cheng wrote: > GCC use `vr` for vector register and `vm` for vector mask register. How does that even work? Aren't multi character strings a set of options? Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

kito-cheng added a comment. GCC use `vr` for vector register and `vm` for vector mask register. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98616/new/ https://reviews.llvm.org/D98616 ___ cfe-commits ma

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

jrtc27 added a comment. This seems like the obvious choice for the constraint, but it would be good to ensure there's consensus with GCC people, especially since their assembly constraints are intimately tied to their instruction patterns (or, really, the assembly constraints just expose those

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

HsiangKai created this revision. HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01. Herald added subscribers: StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27,