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Closed by commit rG3f78605a8cb1: [PowerPC] Add paired vector load and store
builtins and intrinsics (authored by bsaleil).
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rG LLVM Github Monorepo
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saghir accepted this revision.
saghir added a comment.
LGTM.
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amyk accepted this revision.
amyk added a comment.
This revision is now accepted and ready to land.
Thanks for fixing for tests and formatting. LGTM if there are no other concerns.
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bsaleil updated this revision to Diff 303973.
bsaleil added a comment.
Simplify control flow and improve test cases
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Files:
clang/include/clang/Basic/Builtin
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:2658
+ return false;
+}
+
There's alot of nested `if`s, would it be possible to refactor to have some
early exits instead?
Comment at: llvm/test/CodeGen/Power
bsaleil updated this revision to Diff 303540.
bsaleil added a comment.
Fix unaligned load/store select
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Files:
clang/include/clang/Basic/BuiltinsPPC.def
cl
bsaleil updated this revision to Diff 303152.
bsaleil added a comment.
Rebase patch and add Sema check test case for the builtins
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bsaleil updated this revision to Diff 303132.
bsaleil added a comment.
Add support for the paired load/store intrinsics in `PPCLoopInstrFormPrep`
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bsaleil updated this revision to Diff 302983.
bsaleil added a comment.
Add builtin tests
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Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGe
bsaleil created this revision.
bsaleil added reviewers: nemanjai, amyk, saghir, lei.
bsaleil added projects: LLVM, PowerPC.
Herald added subscribers: llvm-commits, cfe-commits, shchenz, kbarton,
hiraditya.
Herald added a project: clang.
bsaleil requested review of this revision.
This patch adds t
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