[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-11-06 Thread Elvina Yakubova via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rG93b99728b167: [AArch64] Add pipeline model for HiSilicon's TSV110 (authored by Elvina). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://rev

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-11-05 Thread Elvina Yakubova via Phabricator via cfe-commits
Elvina added a comment. @SjoerdMeijer thanks for the review! @bryanpkc does everything look fine? Can I commit it? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-comm

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-30 Thread Sjoerd Meijer via Phabricator via cfe-commits
SjoerdMeijer accepted this revision. SjoerdMeijer added a comment. This revision is now accepted and ready to land. I haven't checked the instruction descriptions in detail, but the overall structure looks good to me. Perhaps wait a day with committing in case @bryanpkc has more comments. CHAN

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-29 Thread Elvina Yakubova via Phabricator via cfe-commits
Elvina marked 6 inline comments as done. Elvina added inline comments. Comment at: clang/test/Driver/aarch64-cpus.c:298 +// RUN: %clang -target aarch64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s +// RUN: %clang -target aarch64 -mlittle-endian -mcpu=tsv110

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-29 Thread Elvina Yakubova via Phabricator via cfe-commits
Elvina updated this revision to Diff 301821. Elvina marked 2 inline comments as done. Elvina added a comment. Merged all into one AArch64SchedTSV110.td, removed aarch64-cpus.c test from this patch CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-29 Thread Bryan Chan via Phabricator via cfe-commits
bryanpkc added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:9 +// +// This file defines the machine model for ARM Huawei TSV110 to support +// instruction scheduling and other instruction cost heuristics. I suggest deleting the word

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-29 Thread Sjoerd Meijer via Phabricator via cfe-commits
SjoerdMeijer added inline comments. Comment at: clang/test/Driver/aarch64-cpus.c:298 +// RUN: %clang -target aarch64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s +// RUN: %clang -target aarch64 -mlittle-endian -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -chec

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-29 Thread Elvina Yakubova via Phabricator via cfe-commits
Elvina added a comment. Gentle ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89972/new/ https://reviews.llvm.org/D89972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-23 Thread Elvina Yakubova via Phabricator via cfe-commits
Elvina added a comment. Failure on test "linux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp" looks bogus. I found the same cases https://reviews.llvm.org/D89895 and https://reviews.llvm.org/D89964. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

2020-10-22 Thread Elvina Yakubova via Phabricator via cfe-commits
Elvina created this revision. Elvina added reviewers: bryanpkc, kristof.beyls, t.p.northover, SjoerdMeijer. Elvina added projects: LLVM, clang. Herald added subscribers: cfe-commits, jfb, hiraditya. Elvina requested review of this revision. This patch adds the scheduling and cost model for TSV110.