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Conanap marked an inline comment as done.
Closed by commit rG331dcc43eac2: [PowerPC] Implemented Vector Load with Zero
and Signed Extend Builtins (authored by Conanap).
nemanjai accepted this revision.
nemanjai added a comment.
LGTM aside from a couple of minor nits.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13405
+ // This combine is only eligible for a BUILD_VECTOR of v1i128.
+ // Other return types are not valid for the LXVR
amyk added a comment.
I realized I didn't put a comment on this earlier but this overall LGTM, but I
think it would be good to see if @nemanjai has any additional comments on this
patch.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82502/new/
ht
amyk accepted this revision.
amyk added inline comments.
This revision is now accepted and ready to land.
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:703
+vector signed __int128 test_vec_xl_sext_i8(void) {
+ // CHECK: load i8
+ // CHECK: sext i8
It
Conanap updated this revision to Diff 283061.
Conanap marked 2 inline comments as done.
Conanap added a comment.
Clang formatted relevant lines, combined LE and BE tests as they produced the
same ASM.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D8
NeHuang added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13422
+ return DAG.getMemIntrinsicNode(PPCISD::LXVRZX, dl,
+DAG.getVTList(MVT::v1i128, MVT::Other),
+LoadOps, MemoryType, LD->get
Conanap updated this revision to Diff 281974.
Conanap marked 2 inline comments as done.
Conanap removed a reviewer: power-llvm-team.
Conanap added a comment.
Herald added a subscriber: kbarton.
Some updates on formatting and updated to match an updated test file.
Repository:
rG LLVM Github Mon
amyk added a comment.
Could we also elaborate in the description on how we are utilizing the new load
instructions for zero extend case but not the sign extend case?
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14197
+
+ SDValue LoadOps[] = {LD->getChain(), LD->getB
Conanap updated this revision to Diff 281035.
Conanap added a comment.
Included sext test case.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82502/new/
https://reviews.llvm.org/D82502
Files:
clang/lib/Headers/altivec.h
clang/test/CodeGen/buil
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156
+
+ // This transformation is only valid if the we are loading either a byte,
+ // halfword, word, or doubleword.
Conanap wrote:
> NeHuang wrote:
> > nit: if we are loading
Conanap added a comment.
Addressed formatting comments
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156
+
+ // This transformation is only valid if the we are loading either a byte,
+ // halfword, word, or doubleword.
NeHuang wrote:
> nit: if we
Conanap updated this revision to Diff 280597.
Conanap marked 2 inline comments as done.
Conanap retitled this revision from "[PowerPC][Power10] Implement Load VSX
Vector and Sign Extend and Zero Extend" to "[PowerPC] Implement Load VSX Vector
and Sign Extend and Zero Extend".
Conanap edited the
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