[PATCH] D70088: [ARM,MVE] Add intrinsics for contiguous load/stores.

2019-11-13 Thread Dave Green via Phabricator via cfe-commits
dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. OK. vldr and vld1 working differently for Neon under BE, if I'm remembering correctly. LGTM then. Comment at: clang/utils/TableGen/MveEmitter.cpp:475 // Mostly, when a

[PATCH] D70088: [ARM,MVE] Add intrinsics for contiguous load/stores.

2019-11-13 Thread Simon Tatham via Phabricator via cfe-commits
simon_tatham added a comment. Yes, `vld1` has the same semantics as `vldrw_*32` or `vldrh_*16` or `vldrb_*8`. It's just a convenience alias that makes polymorphism easier – if I remember rightly the intended use case was people writing MVE intrinsics inside C++ templates. Repository: rG LLV

[PATCH] D70088: [ARM,MVE] Add intrinsics for contiguous load/stores.

2019-11-13 Thread Dave Green via Phabricator via cfe-commits
dmgreen added a comment. Very nice Just to check, we don't have to care about big endian here? Is just works OK because the rest of llvm handles it OK? (I'm not sure if a vld1 is different to a vldr in big endian, for example). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION