This revision was automatically updated to reflect the committed changes.
Closed by commit rL314452: [AMDGPU] Allow flexible register names in inline asm
constraints (authored by yaxunl).
Changed prior to commit:
https://reviews.llvm.org/D37568?vs=116383&id=117037#toc
Repository:
rL LLVM
ht
b-sumner accepted this revision.
b-sumner added a comment.
This revision is now accepted and ready to land.
LGTM. I think we can leave immediates to another patch.
https://reviews.llvm.org/D37568
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yaxunl marked an inline comment as done.
yaxunl added a comment.
Ping.
Brian, Stas,
Can you review this since Matt is on vacation? Thanks.
https://reviews.llvm.org/D37568
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yaxunl marked an inline comment as done.
yaxunl added inline comments.
Comment at: test/Sema/inline-asm-validate-amdgpu.cl:74
+__asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "=v[1:2]"(ci) :
"v[3:4]"(ai), "v[5:6]"(bi) : ); //expected-error {{invalid output constraint
'=v[1:2
yaxunl updated this revision to Diff 116383.
yaxunl marked 4 inline comments as done.
yaxunl edited the summary of this revision.
yaxunl added a comment.
Fix typo.
https://reviews.llvm.org/D37568
Files:
lib/Basic/Targets/AMDGPU.h
test/CodeGenOpenCL/amdgcn-inline-asm.cl
test/Sema/inline-as
yaxunl marked 2 inline comments as done.
yaxunl added inline comments.
Comment at: lib/Basic/Targets/AMDGPU.h:194
+Info.setAllowsRegister();
+Name = S.data() - 1;
+return true;
arsenm wrote:
> I'm not sure I understand these data() - 1s.
The caller o
arsenm added inline comments.
Comment at: lib/Basic/Targets/AMDGPU.h:124
+ /// {sn}, {s[n]}
+ /// {S} , wheere S is a special register name
+ {v[n:m]}
Typo wheere
Comment at: lib/Basic/Targets/AMDGPU.h:194
+Info.setAllowsRegister();
yaxunl updated this revision to Diff 114367.
yaxunl edited the summary of this revision.
yaxunl added a comment.
Allow {v[n]} and {s[n]}. Add more tests.
https://reviews.llvm.org/D37568
Files:
lib/Basic/Targets/AMDGPU.h
test/CodeGenOpenCL/amdgcn-inline-asm.cl
test/Sema/inline-asm-validate
yaxunl added a comment.
In https://reviews.llvm.org/D37568#863735, @b-sumner wrote:
> The assembler accepts v[N] in addition to vN. I'm not sure if that is needed
> here.
Then we'd better also allow that in constraints to avoid confusion of users.
https://reviews.llvm.org/D37568
b-sumner added a comment.
The assembler accepts v[N] in addition to vN. I'm not sure if that is needed
here.
https://reviews.llvm.org/D37568
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yaxunl updated this revision to Diff 114223.
yaxunl marked 3 inline comments as done.
yaxunl edited the summary of this revision.
yaxunl added a comment.
Revised by Matt's comments.
https://reviews.llvm.org/D37568
Files:
lib/Basic/Targets/AMDGPU.h
test/CodeGenOpenCL/amdgcn-inline-asm.cl
t
yaxunl added inline comments.
Comment at: test/Sema/inline-asm-validate-amdgpu.cl:38
+__asm("v_add_f32_e32 v1, v2, v3" : "=v1"(ci) : "v2"(ai), "v3"(bi) : ); ///
expected-error {{invalid output constraint '=v1' in asm}}
+__asm("v_add_f32_e32 v1, v2, v3" : "=v1:2"(ci) : "v
arsenm added inline comments.
Comment at: test/Sema/inline-asm-validate-amdgpu.cl:38
+__asm("v_add_f32_e32 v1, v2, v3" : "=v1"(ci) : "v2"(ai), "v3"(bi) : ); ///
expected-error {{invalid output constraint '=v1' in asm}}
+__asm("v_add_f32_e32 v1, v2, v3" : "=v1:2"(ci) : "v
arsenm added inline comments.
Comment at: test/Sema/inline-asm-validate-amdgpu.cl:38
+__asm("v_add_f32_e32 v1, v2, v3" : "=v1"(ci) : "v2"(ai), "v3"(bi) : ); ///
expected-error {{invalid output constraint '=v1' in asm}}
+__asm("v_add_f32_e32 v1, v2, v3" : "=v1:2"(ci) : "v
yaxunl created this revision.
Herald added subscribers: eraman, t-tye, tpr, dstuttard, nhaehnle, wdng,
kzhuravl.
Currently AMDGPU inline asm only allow "v" and "s" as register names in
constraints.
This patch allows the following register names in constraints: (n, m is
unsigned integer, n < m)
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