This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0571ba8d1b4d: [clang-format] Handle Verilog assertions and
loops (authored by sstwcw).
Changed prior to commit:
https://reviews.llvm.org/D147895?v
HazardyKnusperkeks added inline comments.
Comment at: clang/unittests/Format/TokenAnnotatorTest.cpp:844
"};");
- ASSERT_EQ(Tokens.size(), 44u);
+ ASSERT_EQ(Tokens.size(), 44u) << Tokens;
EXPECT_TOKEN(Tokens[13], tok::kw_requires, TT_RequiresClause);
sstwcw added inline comments.
Comment at: clang/unittests/Format/TokenAnnotatorTest.cpp:844
"};");
- ASSERT_EQ(Tokens.size(), 44u);
+ ASSERT_EQ(Tokens.size(), 44u) << Tokens;
EXPECT_TOKEN(Tokens[13], tok::kw_requires, TT_RequiresClause);
HazardyKnusperkeks accepted this revision.
HazardyKnusperkeks added inline comments.
This revision is now accepted and ready to land.
Comment at: clang/unittests/Format/TokenAnnotatorTest.cpp:844
"};");
- ASSERT_EQ(Tokens.size(), 44u);
+ ASSERT_EQ(Tokens.si
sstwcw created this revision.
sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, owenpan, rymiel.
Herald added projects: All, clang, clang-format.
Herald added a subscriber: cfe-commits.
sstwcw requested review of this revision.
Assert statements in Verilog can optionally have an else par