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Closed by commit rG92b2be39656b: [clang-format] Handle enum in Verilog
(authored by sstwcw).
Changed prior to commit:
https://reviews.llvm.org/D147328?vs=510031&id=5
owenpan accepted this revision.
owenpan added inline comments.
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:1712
break;
- // This only applies for C++.
- if (!Style.isCpp()) {
+ // This only applies for C++ and Verilog.
+ if (!Style.isCpp() &&
sstwcw created this revision.
Herald added projects: All, clang, clang-format.
Herald added a subscriber: cfe-commits.
Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay.
sstwcw requested review of this revision.
Verilog has enum just like C.
Repository:
rG LLVM Github
