[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-10 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 521115. pranavk added a comment. [AArch64] Change shouldSinkOperand to allow bitselect instructions Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 Files: llvm/lib/

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-10 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 521114. pranavk added a comment. [AArch64][InstCombine] Bail out for bitselect instructions Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 Files: llvm/lib/Transfor

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-10 Thread Pranav Kant via Phabricator via cfe-commits
pranavk planned changes to this revision. pranavk added a comment. I agree. I changed the implementation to not introduce the intrinsic. I will need another change in InstCombine to handle case #1 mentioned on github bug report. I will have separate patch for it changing InstCombine. Thanks Re

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-10 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 521040. pranavk edited the summary of this revision. pranavk added a comment. Change shouldSinkOperand to allow backend to generate bitselect instructions Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-02 Thread Dave Green via Phabricator via cfe-commits
dmgreen added a comment. My preference would be for fixing the code we have, not introducing new intrinsics. Intrinsics act as black-boxes for the optimizer, and I'm pretty sure I've heard of cases in the past of the compiler optimizing the or/and/xor's to nicer sequences of instructions. It wo

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-01 Thread Eli Friedman via Phabricator via cfe-commits
efriedma added a comment. I guess I should note both the examples in https://github.com/llvm/llvm-project/issues/49305 could probably be fixed in other ways... we have heuristics to, for example, sink logic ops into loops when it's profitable. But that requires someone to notice the specific i

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-05-01 Thread Eli Friedman via Phabricator via cfe-commits
efriedma added a reviewer: dmgreen. efriedma added subscribers: bsmith, paulwalker-arm, lenary. efriedma added a comment. The primary tradeoff here is that existing optimizations won't understand the intrinsic... for example, we can't constant-fold, or automatically invert the mask. But making

[PATCH] D147266: [AArch64] Add IR intrinsics for vbsl* C intrinsics

2023-03-30 Thread Pranav Kant via Phabricator via cfe-commits
pranavk created this revision. Herald added subscribers: hiraditya, kristof.beyls. Herald added a project: All. pranavk requested review of this revision. Herald added projects: clang, LLVM. Herald added subscribers: llvm-commits, cfe-commits. VBSL intrinsics can be found here: https://developer.