pranavk updated this revision to Diff 521115.
pranavk added a comment.
[AArch64] Change shouldSinkOperand to allow bitselect instructions
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pranavk updated this revision to Diff 521114.
pranavk added a comment.
[AArch64][InstCombine] Bail out for bitselect instructions
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rG LLVM Github Monorepo
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pranavk planned changes to this revision.
pranavk added a comment.
I agree. I changed the implementation to not introduce the intrinsic. I will
need another change in InstCombine to handle case #1 mentioned on github bug
report. I will have separate patch for it changing InstCombine. Thanks
Re
pranavk updated this revision to Diff 521040.
pranavk edited the summary of this revision.
pranavk added a comment.
Change shouldSinkOperand to allow backend to generate bitselect instructions
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dmgreen added a comment.
My preference would be for fixing the code we have, not introducing new
intrinsics. Intrinsics act as black-boxes for the optimizer, and I'm pretty
sure I've heard of cases in the past of the compiler optimizing the
or/and/xor's to nicer sequences of instructions. It wo
efriedma added a comment.
I guess I should note both the examples in
https://github.com/llvm/llvm-project/issues/49305 could probably be fixed in
other ways... we have heuristics to, for example, sink logic ops into loops
when it's profitable. But that requires someone to notice the specific i
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efriedma added a comment.
The primary tradeoff here is that existing optimizations won't understand the
intrinsic... for example, we can't constant-fold, or automatically invert the
mask. But making
pranavk created this revision.
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VBSL intrinsics can be found here:
https://developer.