[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG96a7e057567d: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANG

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. I also understand that Rocket and SCR-1 support zicsr and zifencei in all standard configurations (and their respective repos seem to confirm this). Repository: rG LLVM Github Monorepo CHA

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

craig.topper created this revision. craig.topper added reviewers: reames, asb, kito-cheng, jrtc27, philipp.tomsich, dnpetrov-sc. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, t