[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

mamrami added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:1 +! Test -emit-obj (RISC-V 64) + sunshaoce wrote: > mamrami wrote: > > sunshaoce wrote: > > > awarzynski wrote: > > > > mamrami wrote: > > > > > Hi :) > > > > > It seems like the test

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce added a subscriber: DavidSpickett. sunshaoce added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:1 +! Test -emit-obj (RISC-V 64) + mamrami wrote: > sunshaoce wrote: > > awarzynski wrote: > > > mamrami wrote: > > > > Hi :) > > > > It s

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

mamrami added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:1 +! Test -emit-obj (RISC-V 64) + sunshaoce wrote: > awarzynski wrote: > > mamrami wrote: > > > Hi :) > > > It seems like the test fails: > > > https://buildkite.com/llvm-project/prem

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:1 +! Test -emit-obj (RISC-V 64) + awarzynski wrote: > mamrami wrote: > > Hi :) > > It seems like the test fails: > > https://buildkite.com/llvm-project/premerge-checks/builds/141302

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:1 +! Test -emit-obj (RISC-V 64) + mamrami wrote: > Hi :) > It seems like the test fails: > https://buildkite.com/llvm-project/premerge-checks/builds/141302#0186e55e-199e-401d-ab9f-

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

mamrami added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:1 +! Test -emit-obj (RISC-V 64) + Hi :) It seems like the test fails: https://buildkite.com/llvm-project/premerge-checks/builds/141302#0186e55e-199e-401d-ab9f-9f3d47ec87af I see it in

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

This revision was automatically updated to reflect the committed changes. sunshaoce marked an inline comment as done. Closed by commit rG36278b735fa1: [Flang][RISCV] Emit target features for RISC-V (authored by sunshaoce). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce updated this revision to Diff 505363. sunshaoce added a comment. Address @MaskRay's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145883/new/ https://reviews.llvm.org/D145883 Files: clang/lib/Driver/ToolChains/Flang.cpp flang

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

MaskRay added inline comments. Comment at: clang/lib/Driver/ToolChains/Flang.cpp:108 case llvm::Triple::aarch64: [[fallthrough]]; + case llvm::Triple::riscv64: Remove `[[fallthrough]]` and just list the 3 `case` consecutively. Comment

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce added a comment. Any other opinions? If not, I will land it later. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145883/new/ https://reviews.llvm.org/D145883 ___ cfe-commits mailing list cfe-co

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

kiranchandramohan accepted this revision. kiranchandramohan added a comment. LG. Please wait for and OK from @jrtc27. Comment at: clang/lib/Driver/ToolChains/Flang.cpp:112-114 + case llvm::Triple::riscv64: +getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); +

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/target-cpu-features-invalid.f90:13 +! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor) +! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this ta

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

jrtc27 added inline comments. Comment at: flang/test/Driver/target-cpu-features-invalid.f90:13 +! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor) +! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski accepted this revision. awarzynski added a comment. This revision is now accepted and ready to land. LGTM, thanks for contributing! Please wait for the other reviewers to confirm that they are happy with these changes. Comment at: flang/test/Driver/target-cpu-featu

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:7 +! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \ +! RUN: -target-feature +d -target-feature +c -emit-obj %s -o %t.o +! RUN: llvm-readelf -h %t.o | FileCheck %s awarzynski w

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:7 +! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \ +! RUN: -target-feature +d -target-feature +c -emit-obj %s -o %t.o +! RUN: llvm-readelf -h %t.o | FileCheck %s jrtc27 wrot

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

jrtc27 added inline comments. Comment at: clang/lib/Driver/ToolChains/Flang.cpp:112-114 + case llvm::Triple::riscv64: +getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); +break; kiranchandramohan wrote: > jrtc27 wrote: > > mnadeem wrote: > > >

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce updated this revision to Diff 504756. sunshaoce marked 2 inline comments as done. sunshaoce added a comment. Add `target-cpu-features-invalid.f90` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145883/new/ https://reviews.llvm.org/D145883

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:12 + +! CHECK: Flags: 0x5, RVC, double-float ABI +end program sunshaoce wrote: > awarzynski wrote: > > awarzynski wrote: > > > For those of us less familiar with RISC-V - could you

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce marked 5 inline comments as done. sunshaoce added inline comments. Comment at: flang/test/Driver/target-cpu-features.f90:33 ! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU ! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +sup

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/target-cpu-features.f90:1 -! REQUIRES: aarch64-registered-target, x86-registered-target +! REQUIRES: aarch64-registered-target, x86-registered-target, riscv-registered-target vzakhari wrote: > Can

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

vzakhari added inline comments. Comment at: flang/test/Driver/target-cpu-features.f90:1 -! REQUIRES: aarch64-registered-target, x86-registered-target +! REQUIRES: aarch64-registered-target, x86-registered-target, riscv-registered-target Can we split this test

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:12 + +! CHECK: Flags: 0x5, RVC, double-float ABI +end program awarzynski wrote: > awarzynski wrote: > > For those of us less familiar with RISC-V - could you explain what's > > sign

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce updated this revision to Diff 504695. sunshaoce added a comment. Add `REQUIRES` in tests Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145883/new/ https://reviews.llvm.org/D145883 Files: clang/lib/Driver/ToolChains/Flang.cpp flang/te

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:2 +! Test -emit-obj (RISC-V 64) + +! RUN: rm -f %t.o Missing `REQUIRES: ` - this test won't work unless the RISC-V backend is available. Comment at: flang/test/

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce updated this revision to Diff 504672. sunshaoce marked an inline comment as done. sunshaoce added a comment. Address @awarzynski's comment. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145883/new/ https://reviews.llvm.org/D145883

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/code-gen-rv64.f90:12 + +! CHECK: Flags: 0x5, RVC, double-float ABI +end program For those of us less familiar with RISC-V - could you explain what's significant about this line? For example, [[ htt

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce updated this revision to Diff 504616. sunshaoce added a comment. Add test Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145883/new/ https://reviews.llvm.org/D145883 Files: clang/lib/Driver/ToolChains/Flang.cpp flang/test/Driver/code-

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

kiranchandramohan added inline comments. Comment at: clang/lib/Driver/ToolChains/Flang.cpp:112-114 + case llvm::Triple::riscv64: +getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); +break; jrtc27 wrote: > mnadeem wrote: > > identical code, cou

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added a comment. Herald added a subscriber: jobnoorman. > Fix the issue of .o file generated by Flang with Flags info is 0x0 under > RISC-V. TBH, I don't see how this is addressed in this patch. If that's something that this patch is intending to fix, then there should be a regressio

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce updated this revision to Diff 504548. sunshaoce added a comment. Based on everyone's comments, I merged the test into `target-cpu-features.f90` and only kept the generic `-target-feature`. At the same time, I removed the `switch (TC.getArch())` and passed the test on x86 and RISC-V 64.

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

jrtc27 added inline comments. Comment at: flang/test/Driver/target-features.f90:1 +! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-RV64 awarzynski wrote: > jrtc27 wrote: > > awarzynski wrote:

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added inline comments. Comment at: flang/test/Driver/target-features.f90:1 +! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-RV64 jrtc27 wrote: > awarzynski wrote: > > What happens i

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

jrtc27 added inline comments. Comment at: flang/test/Driver/target-features.f90:1 +! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-RV64 awarzynski wrote: > What happens if the RISC-V backend i

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

awarzynski added a comment. Why does "flang/test/Driver/target-features.f90" list all RISC-V features? Why not use https://github.com/llvm/llvm-project/blob/main/flang/test/Driver/target-cpu-features.f90 instead? Comment at: flang/test/Driver/target-features.f90:1 +! RUN: %

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

jrtc27 added inline comments. Comment at: clang/lib/Driver/ToolChains/Flang.cpp:112-114 + case llvm::Triple::riscv64: +getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); +break; mnadeem wrote: > identical code, could just do a fallthrough Why

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

mnadeem added inline comments. Comment at: clang/lib/Driver/ToolChains/Flang.cpp:112-114 + case llvm::Triple::riscv64: +getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); +break; identical code, could just do a fallthrough Repository: rG L

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

mnadeem added a comment. There is an existing test `flang/test/Driver/target-cpu-features.f90` added in D137995 Would it be better to add RISCV to that file? or perhaps rename the tests to have target specific files? Repository: rG LLVM Github Monorepo CH

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

sunshaoce created this revision. sunshaoce added reviewers: awarzynski, klausler, clementval, sscalpone, craig.topper, jrtc27, kito-cheng. Herald added subscribers: VincentWu, vkmr, evandro, luismarques, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, simoncook, arichar