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Closed by commit rGa6aaa969f7ca: [AArch64] Assembly support for FEAT_LRCPC3
(authored by tmatheson).
Changed prior to commit:
https://reviews.llvm.org/D138579?vs=478
tmatheson updated this revision to Diff 478001.
tmatheson marked 3 inline comments as done.
tmatheson added a comment.
Address comments and change instruction names
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138579/new/
https://reviews.llvm.org/
tschuett added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64.td:510
+def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3",
+"true", "Enable Armv8.9-A RCPC instructions added to A64 and Advanced SIMD
and floating-point instruction set (FEAT_LRCPC3)",
-
lenary added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:8572
+ def STLR_x_64 : BaseLRCPC3IntegerLoadStore<0b11, 0b10, (outs GPR64sp:$Rn_wb)
, (ins GPR64:$Rt, GPR64sp:$Rn), "stlr" , "\t$Rt, [$Rn, #-8]!", "$Rn =
$Rn_wb">; /* PUSH register
dmgreen added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:11772
+ : I,
+Sched<[]> {
+ bits<5> Rt;
One extra nit: Can we add a scheduling description? These sound like they can
use WriteAtomic.
Repository:
rG LLVM
lenary accepted this revision.
lenary added a comment.
This revision is now accepted and ready to land.
Some comment nits that you can fixup on commit.
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:3913
+// are post-indexed, and the immediate values are not inside the
tmatheson created this revision.
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This patch implements assembly support for the 202
