[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-24 Thread Guozhi Wei via Phabricator via cfe-commits
Carrot abandoned this revision. Carrot added a comment. Thanks for the clarification, I will propose another patch for my purpose. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D132531/new/ https://reviews.llvm.org/D132531 _

[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-24 Thread Eli Friedman via Phabricator via cfe-commits
efriedma added a comment. > A reserved physical register doesn't mean it can't be used by > compiler/linker, it just means it can't be used by register allocator, see > the comments in TargetRegisterInfo::getReservedRegs(). The target feature to "reserve" a register is meant to be "don't use th

[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-24 Thread Guozhi Wei via Phabricator via cfe-commits
Carrot added a comment. I want to reserve most of the physical registers, so only a small number of registers can be used by register allocator. Then I can write small test cases to simulate high register pressure situation, it will be much easier to test and debug register allocation changes.

[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-24 Thread Kristof Beyls via Phabricator via cfe-commits
kristof.beyls added a comment. See https://reviews.llvm.org/D56305 and https://reviews.llvm.org/D48580 for previous related discussions. I think it would be helpful to understand the use case for being able to reserve x8, x16, x17 and x19 better. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-24 Thread Guozhi Wei via Phabricator via cfe-commits
Carrot added a comment. A reserved physical register doesn't mean it can't be used by compiler/linker, it just means it can't be used by register allocator, see the comments in TargetRegisterInfo::getReservedRegs(). The most common example is the stack pointer. So when we reserve X8, X16, X17 a

[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-23 Thread Kristof Beyls via Phabricator via cfe-commits
kristof.beyls added a comment. My understanding is that X8, X16, X17 and X19 cannot be reserved because the code generator in places will make use of them. For example, using X19 as a base register in some cases. X16 and X17 are defined by the ABI to potentially be clobbered on function calls &

[PATCH] D132531: [AArch64] Reserve more physical registers

2022-08-23 Thread Guozhi Wei via Phabricator via cfe-commits
Carrot created this revision. Carrot added a reviewer: dmgreen. Herald added subscribers: hiraditya, kristof.beyls. Herald added a project: All. Carrot requested review of this revision. Herald added subscribers: llvm-commits, cfe-commits, MaskRay. Herald added projects: clang, LLVM. Reserved phys