frasercrmck updated this revision to Diff 402572.
frasercrmck added a comment.
Herald added a subscriber: pcwang-thead.
rebase
take minimum from zvl extensions
allow backend options to override attribute values
add extra testing
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101
+ } else {
+RVVBitsMin = RVVVectorBitsMinOpt;
+RVVBitsMax = RVVVectorBitsMaxOpt;
frasercrmck wrote:
> frasercrmck wrote:
> > craig.topper wrote:
> > > If cla
frasercrmck added inline comments.
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Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101
+ } else {
+RVVBitsMin = RVVVectorBitsMinOpt;
+RVVBitsMax = RVVVectorBitsMaxOpt;
-
frasercrmck added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101
+ } else {
+RVVBitsMin = RVVVectorBitsMinOpt;
+RVVBitsMax = RVVVectorBitsMaxOpt;
craig.topper wrote:
> If clang always emits the attribute, are these options
craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101
+ } else {
+RVVBitsMin = RVVVectorBitsMinOpt;
+RVVBitsMax = RVVVectorBitsMaxOpt;
If clang always emits the attribute, are these options effectively dead for
frasercrmck added inline comments.
Comment at: clang/lib/Basic/Targets/RISCV.cpp:349
+ unsigned VLENMax = 65536;
+ return std::make_pair(VLENMin / 64, VLENMax / 64);
+}
craig.topper wrote:
> Should we move RVVBitsPerBlock to RISCVTargetParser.def? Or some other
frasercrmck updated this revision to Diff 369416.
frasercrmck marked 2 inline comments as done.
frasercrmck added a comment.
Herald added a subscriber: dexonsmith.
- rebase
- move V VLEN bits-per-block (64), min (128), max (65536) defines into
TargetParser.h
- clean up assertions
Repository:
kito-cheng added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:106
+ assert(RVVBitsMin % 128 == 0 &&
+ "RVV requires vector length in multiples of 128!");
+ assert(RVVBitsMax % 128 == 0 &&
RISC-V require VLEN in power of 2, m
craig.topper added inline comments.
Comment at: clang/lib/Basic/Targets/RISCV.cpp:349
+ unsigned VLENMax = 65536;
+ return std::make_pair(VLENMin / 64, VLENMax / 64);
+}
Should we move RVVBitsPerBlock to RISCVTargetParser.def? Or some other place
that can be s
frasercrmck added a comment.
Ah no, my mistake. This would be a drop in functionality if `getMaxVScale` is
removed, since its replacement only checks the IR attribute and will not be
affected by our backend flags.
Repository:
rG LLVM Github Monorepo
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https://revie
frasercrmck added a comment.
This may be as far as we can take this patch without exposing RVV vectors bit
control to the user/driver and having to worry about the concerns that spring
from that: linking objects compiled with different RVV vector bits options,
LTO, etc.
I believe that with the
frasercrmck updated this revision to Diff 367232.
frasercrmck added a comment.
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update usage in vein of AArch64:
- use vscale_range attribute to determine RVV vector bits min/max values
- if no attribute is present, u
frasercrmck created this revision.
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arcbbb, khchen.
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