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NeHuang added a comment.
@jroelofs committed `f6769b663a0d4432b5e00e0c03904a5dfba7b077` to move the
backend test cases from `CodeGen` -> `CodeGen/PowerPC` so they don't fail when
the PPC backend isn't built.
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Conanap added a comment.
issue should be fixed now; pushed with this:
https://reviews.llvm.org/D106130#change-PZi4uueeCg9i
(I just had to move the test files into the `PowerPC` folder).
Will continue to monitor
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Conanap added a comment.
I'm aware of the getting target issue; the fix will be up soon.
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This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3434ac9e3902: [PowerPC] Store, load, move from and to
registers related builtins (authored by Conanap).
Changed prior to commit:
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Conanap updated this revision to Diff 359945.
Conanap added a comment.
Fixed a typo
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clang/lib/Basic/Tar
Conanap updated this revision to Diff 359850.
Conanap added a comment.
Changed flags for intrinsic of dcbtt and dcbtstt
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nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.
LGTM.
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Conanap updated this revision to Diff 359516.
Conanap marked an inline comment as done.
Conanap added a comment.
Moved pattern to a more appropriate place, updated test cases
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Conanap marked 4 inline comments as done.
Conanap added a comment.
Addressed comments
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+ // CHECK-LABEL: @test_lwarx
// CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}",
"=r,*Z,~{memor
Conanap updated this revision to Diff 359433.
Conanap marked an inline comment as done.
Conanap added a comment.
Updated test cases
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lei added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+ // CHECK-LABEL: @test_lwarx
// CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}",
"=r,*Z,~{memory}"(i32* %a)
return __lwarx(a);
where is
nemanjai added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4072
+
+def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
+ (STXSIWX f64:$XT, ForceXForm:$dst)>;
I just realized this is in the wrong place. STXSIWX was added in Power8
Conanap updated this revision to Diff 359380.
Conanap added a comment.
Updated a test case
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clang/lib/Ba
Conanap updated this revision to Diff 359322.
Conanap marked 5 inline comments as done.
Conanap added a comment.
Added non-vsx pattern for stfiw, extra testline for that pattern,
some nits
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nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.
This is getting close to approval. The newly added `__stfiw` needs to be fixed
and some nits need to be addressed.
Comment at: clang/lib/Sema/SemaChecking.cpp:
Conanap updated this revision to Diff 359259.
Conanap added a comment.
Updated lharx and lbarx to inline asm implementation, implemented stfiw.
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nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.
Taking this off the review queue until `lharx/lbarx` are changed to emit inline
asm in line with `lwarx/ldarx`.
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Conanap updated this revision to Diff 359104.
Conanap added a comment.
Changed more xoaddr to ForceXForm
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Conanap updated this revision to Diff 359097.
Conanap marked 2 inline comments as done.
Conanap added a comment.
Changed xoaddr, removed extws, changed check prefix
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lei added inline comments.
Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569
}
-
nit: un-related line deletion
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:5449
+ def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A),
+ (STH
Conanap updated this revision to Diff 359066.
Conanap added a comment.
Added more tests, corrected sema checking and intrinsic flag
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nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.
We have encountered an issue with `lwarx/ldarx` that required that they emit
inline asm rather than an intrinsic. What makes `lbarx/lharx` different?
Comment a
lei added inline comments.
Comment at: clang/lib/Sema/SemaChecking.cpp:3371
+return SemaFeatureCheck(*this, TheCall, "extdiv",
+diag::err_ppc_builtin_only_on_arch, "8");
#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
need tests
lei added inline comments.
Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569
+ def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrWriteMem]>;
+ def int_ppc_lharx : GCCBuiltin<"__builtin_ppc_lharx">,
+ Intrinsic<[llvm_i32
Conanap updated this revision to Diff 358738.
Conanap marked an inline comment as done.
Conanap added a comment.
Added more sema checking, test case update
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lei added a comment.
please add sema checking for pwr8 builtins.
Comment at:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll:80
+declare i32 @llvm.ppc.lharx(i8*)
+define dso_local signext i16 @test_lharx(i16* %a) local_unnamed_addr #0 {
+; CHECK-64-LAB
Conanap created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
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This patch implements store, load, move from and to registers relate
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